Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Yasuhiro Ishii

Hideki Murayama

Takehisa Hayashi

Naoki Hamanaka

Tetsuhiko Okada

Masabumi Shibata

Daisuke Sasaki

Hiroshi Yashiro

Masahiko Yamauchi

Kazuo Horikawa

Kazuo Takaragi

Naohiko Irie

Tetsuya Mochida

Youichi Tanaka

Akira Yamagiwa

Akinobu Shimada

Masafumi Nozawa

Tsutomu Nakamura

Kenichi Ishibashi

Tokuhiro Tsukiyama

Masahiro Kitano

Fujio Fujita

Atsushi Ugajin

Toshifumi Nishimura

Tsutomu Goto

Katsuharu Kakuse

Kiyoshi Yata

Atuo Kobayashi

Yasushi Kuba

An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.

Information processing apparatus

Memory managing method used in adding memory and information processing apparatus

In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the following manner. For an access request to a main memory, the access request is transferred to all processor units and one memory unit storing the data to be accessed. For an access request to a memory mapped register of the input/output device, the access request is broadcast to all input/output units. For an access request to a memory mapped register belonging to any one of the processor units, memory units, and input/output units, the access request is broadcast to all units via the crossbar switch.

Multi-processor system and its network

One or more combinations of an operating data processing machine and a backup data processing machine are connected together to enable backup switching wherein the backup machine takes over the data processing from the operating machine when a failure occurs in the operating machine. In particular, each of the operating and backup machines is connected to one or several system resources, such as data storage or data output devices. The operating processor exclusively occupies the system resources, and when a failure occurs the operating processor is disconnected therefrom. A disconnection completion notice is sent to the backup processor, which then begins to exclusively occupy the system resources for performing ongoing data processing that would have been performed by the operating processor had the failure not occurred. When a failure occurs with the operating processor, the data being processed and the data concerning the failure are dumped to an auxiliary memory to facilitate analysis of the failure. Once the failed operating processor is returned to service, it functions as a backup processor that is switched to take over the data processing when a failure occurs in the new operating processor.

Backup switching control system and method

A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

Semiconductor integrated circuit system having function of automatically

A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be linked together for parallel or pipeline processing of the DMA transfer requests. Each start request quad has a pointer for additionally retrieving corresponding command data. The command data is set forth in a number of blocks, each linked to the next one by a pointer. When a DMA processing has been completed, the termination or completion status is entered into a specific entry in a completion list for the corresponding IO device. Thus, a determination can be made as to whether specific IO devices have completed a requested DMA processing. Expansion of the system is accomplished by using combinations of main and sub controllers, where one main controller provides the aforementioned data structures for many sub controllers in order to enable the DMA processing to be performed for IO devices connected to the sub controllers with less frequent access of system main memory and the system bus.

Input/output control method and data processor

In an information processing system having an upper rank apparatus and an external storage device which performs transmission and reception of data between the storage device and the upper rank apparatus, at least one of encryption and decryption of the data by use of an algorithm controlled by a desired data key is performed in the external storage device, while generation, encryption and decryption of the data key are performed on the upper rank apparatus side. By this configuration, the burden of the upper rank apparatus is largely reduced and the secrecy of data stored in the external storage device can be surely kept without spoiling the throughput of the whole system.

File encryption method and file cryptographic system

A cryptographic communication method and system for performing cryptographic communication between a host computer and a given one of plural terminals connected to the host computer by way of a communication network by using a data key designated by the given terminal or the host, wherein the host computer includes a cryptographic processing unit which includes a processing part for performing a public key cryptographic processing by using a pair of a public key and a private key and a common key cryptographic processing by using a common key, and an internal memory for storing master common key and master private key, a storage for recording as user private key information those data that result from the public key cryptographic processing performed by using a master public key on a plurality of user private keys which are in paired relation to user public keys held in the user terminals, respectively, and control means for performing input/output control between the storage and the cryptographic processing means.

Cryptographic communication method and system

Growing community of inventors

Hadano, Japan

Yasuhiro Ishii