Sony Corporation

Nippon Telegraph and Telephone Corporation

Mitsubishi Heavy Industries Bridge & Steel Structures Engineering Co., Ltd.

Yasuhiro Iida

Takashi Yokokawa

Toshiyuki Miyauchi

Kiyofumi Inanaga

Hiroyuki Sogawa

Hideo Suyama

Shigeyoshi Imakoshi

Naoki Yoshimochi

Yutaka Soda

Hidetoshi Kawauchi

Takanori Minamino

Masayoshi Miura

Takashi Horiguti

Kazuhiro Oguchi

Kenichi Kobayashi

Hiroyuki Uchida

Makoto Kobayashi

Takao Nakamura

Kenichi Sato

Yuji Shinohara

Akira Kimura

Masayuki Hattori

Hiroyuki Tanaka

Ryoji Ikegaya

Hiroshi Ogawa

Hiroshi Sakai

Atsushi Kikuchi

Hiroyuki Kamata

Ryo Hasegawa

Takashi Hagiwara

Munekatsu Fukuyama

Tetsuo Sekiya

Norihisa Shirota

Satoru Hori

Kazukuni Takanohashi

Naoya Haneda

Susumu Yabe

Kohei Yamamoto

Kazuhisa Funamoto

Koya Mori

Makiko Kan

Masayuki Hanadate

Yutaka Souda

Kazuyoshi Kihara

Ryutaro Kawamura

Yukio Koike

Hisanobu Nagatomo

Takahsi Yokokawa

Yabe Susumu

Mitsuru Sasano

Hirofumi Inagaki

Shigekuni Kondo

Keiji Kanai

Akira Sakaguchi

Taro Arikawa

Hirohide Kimura

The present invention includes a memory and a processor configured to store, in a storage, a first digital twin in which at least one model defining at least one function of an entity at a given time, and at least one piece of second data that includes, as a constituent element, first data for realizing the function of the entity due to being input to the model are included, create at least one second digital twin by performing predetermined first computation using, as a computation target, at least one first digital twin stored in the storage, and execute computation for arranging the second digital twin in a sandbox for which a predetermined time axis has been set, and realizing a function of an entity indicated by the second digital twin in the sandbox in accordance with the time axis.

Digital twin computing apparatus, digital twin computing method, program and data structure

There may be included: a demodulation section configured to perform, based on a modulated signal transmitted from an associated communication device, amplitude change demodulation and phase change demodulation, and configured to select a demodulated signal demodulated with either one of the amplitude change demodulation and the phase change demodulation; and a modulation section configured to modulate magnetic field generated by the associated communication device.

Communication device, communication system, and communication method

A signal processing device includes: an extraction section configured to extract a signal having a predetermined component from an obtained signal; and a detection section configured to determine a timing of decoding when a modulation part lasting for a first time period and a non-modulation part lasting for a second time period are detected from the signal extracted by the extraction section.

Signal processing device, method of processing signal, and recording medium

The present invention provides a movable breakwater that can do with a small amount of compressed air supplied to raise the buoyant steel pipe. The buoyant steel pipeincludes a buoyancy tankin which gas is filled, an air chamberprovided above the buoyancy tank, a penetration pipethat penetrates through the buoyancy tankand feeds compressed air supplied from a pressure accumulator tankto the air chamber, and an open chamber, whose top side is open, provided above the air chamberand in the buoyant steel pipeat the upper end portion thereof.

Movable breakwater and method of operating movable breakwater

The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P&#xd7;P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P&#xd7;P) 0-matrix. A check node calculatorsimultaneously performs p check node calculations. A variable node calculatorsimultaneously performs p variable node calculations.

Decoding apparatus, decoding method, and program to decode low density parity check codes

A decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device includes, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data. The decoding device decodes second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data. A synchronization detector is configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data. The synchronization detector selects and outputs one of the first decoded data and the second decoded data based on a result of the detection of the boundary.

Decoding device and method, receiving device and method, and program

Disclosed herein is a reception apparatus, including, an orthogonal frequency division multiplexing signal reception section, a first filter section, a subtraction section, a second filter section, a coefficient production section, and a Fast Fourier Transformation mathematic operation section.

Reception apparatus, reception method and program

A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes:

Reception device, control method, and program

A reception device includes: an AGC circuit adapted to control the amplitude of a receive signal; a correction circuit adapted to correct the flutter component in the output signal of the AGC circuit; a synchronization circuit adapted to establish synchronization with the signal whose flutter component has been corrected by the correction circuit; and an equalization circuit adapted to perform an equalization process based on the signal with which synchronization has been established by the synchronization circuit and output the equalized signal, wherein the correction circuit includes a detection circuit, an IIR filter, a gain circuit, a flutter component correction circuit, and a gain control circuit.

Reception device, reception method and program

A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.

Demodulating circuit, demodulating method, program, and receiving device

An information processing apparatus that processes a multiplexed stream including a frame having multiple slots, which is obtained by multiplexing multiple streams containing time information describing times is disclosed. The apparatus includes extracting means for extracting predetermined one or more slots from the frame of the multiplexed stream, storage means for storing data of the slot(s), and frequency dividing means for generating a second clock signal by frequency-dividing a first clock signal by a frequency division ratio N:M based on the number of clocks N corresponding to the time for one frame in the multiplexed stream and the number of clocks M for reading the data of the slot(s) extracted from the one frame from the storage means in the time for the one frame. The data of the slot or slots stored in the storage means is read in synchronization with the second clock signal.

Information processing apparatus and method

The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoderperforms SISO decoding on a signal supplied from a PR-SISO decoderby using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding tableof a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decodervia a deinterleaver. The turbo decoderperforms turbo decoding on the signal output from the 17PP-SISO decoder. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.

Decoding device and method, program recording medium, and program using modulation code encoded in accordance with a variable length table

The present invention relates to a decoding method and a decoding apparatus in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. By using a transformation check matrix obtained by performing one of or both a row permutation and a column permutation on an original check matrix of LDPC (Low Density Parity Check) codes, the LDPC codes are decoded. In this case, by using, as a formation matrix, a P&#xd7;P unit matrix, a quasi-unit matrix in which one or more 1s, which are elements of the unit matrix, are substituted with 0, a shift matrix in which the unit matrix or the quasi-unit matrix is cyclically shifted, a sum matrix, which is the sum of two or more of the unit matrix, the quasi-unit matrix, and the shift matrix, and a P&#xd7;P 0-matrix, the transformation check matrix is represented by a combination of a plurality of the formation matrices. A check node calculatorsimultaneously performs p check node calculations. A variable node calculatorsimultaneously performs p variable node calculations.

Decoding method, decoding apparatus, and program to decode low density parity check codes

The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleavingbefore the second encoding, the sequences are permuted so as not to be mixed with each other.

Encoding device for performing serial concatenated coding

Growing community of inventors

Tokyo, Japan

Yasuhiro Iida