Sharp Kabushiki Kaisha Corporation

Yasuhiro Hotta

Koji Komatsu

Mikiro Okada

Shuichiro Kouchi

Takeshi Nojima

A semiconductor memory of the present invention includes a sense amplifier for amplifying a potential difference between a potential of a first terminal and a potential of a second terminal, a first load gate located between the first terminal and a bit line, and a second load gate located between the second terminal and a reference line. A current flowing to the first load gate is controlled by a potential of the bit line, and a current flowing to the second load gate is controlled by a potential of the reference line.

Apparatus for a semiconductor memory with independent reference voltage

A clock-synchronized read only memory includes: a memory cell and a mode register for setting an operation mode, the clock-synchronized read only memory outputting data stored in the memory cell in the operation mode set in the mode register and in synchronization with a clock signal. The contents of the mode register are set when the data is written to the memory cell, the contents defining the operation mode.

Clock-synchronized read-only memory

A semiconductor memory device includes a main memory section, a redundant memory section, a memory cell selection section, a sensing amplification section, a data replacement section, and a data selection section. The redundant memory section includes a replacement cell data memory section for storing replacement cell data to replace cell data in a prescribed memory cell in the main memory section, and a control signal generation section for generating a control signal based on an input address. The memory cell selection section simultaneously selects prescribed cells as a plurality of memory cells corresponding to a prescribed page in the main memory section based on the input address. The sensing amplification section simultaneously senses cell data corresponding to a selected plurality of memory cells as page data. A supply of the replacement cell data and the control signal from the redundant memory section to the data replacement section is performed in a time period from the time when the input address is determined until a time when the page data to be output from the sensing amplification section is determined.

Semiconductor memory device

The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.

Semiconductor memory using select transistors coupled to sub-bitlines

A semiconductor memory device includes a plurality of memory cells for storing data and a selector for selecting at least one memory cell from the plurality of memory cells based on an address signal. The semiconductor memory device includes a transient detecting unit for outputting a first signal in accordance with a transient of the address signal; and a generator for generating a second signal indicating a wait for accessing a memory cell based on the first signal and a clock signal.

Semiconductor memory device with address signal transition detection

A semiconductor memory device according to the present invention includes: a memory cell array including a plurality of virtual ground lines, a plurality of bit lines, and a plurality of memory cells arranged in a matrix shape; a selection circuit; a first amplifier circuit; a second amplifier circuit; and a first control circuit and a second control circuit. The first control circuit and the second control circuit selectively charge or discharge those of the plurality of virtual ground lines corresponding to one page in accordance with the input address, the first control circuit and the second control circuit performing the charging or discharging independently of each other.

A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector for selecting a row of the memory cell array corresponding to a row address of an input address, and column selector for selecting a plurality of columns of a memory cell array corresponding to a column address of an input address, and also selecting a plurality of columns of a memory cell array corresponding to at least one column address other than a column address of an input address. The device also includes a sense amplifier for sensing data stored in memory cells. The sense amplifier has at least two sense amplifier groups, the sense amplifier groups sensing data read from a plurality of memory cells corresponding to an input address, and data read from a plurality of memory cells corresponding to the row address of an input address and at least one other column address. The device has a page mode for rapidly switching and outputting data from a plurality of memory cells which have been read in parallel to sense amplifier in accordance with an input address.

Semiconductor memory device with fast successive read operation

The semiconductor memory device includes two sense amplifiers provided corresponding to data lines and a switching circuit for selectively connecting any two among the data lines to the two sense amplifiers, respectively. The data stored in one of the memory cells is amplified to be transmitted to an output buffer via the data line connected to one of the sense amplifiers. In parallel with this operation, the data stored in a next memory cell is amplified via the data line connected to another sense amplifier so as to be made valid. In this manner, after the data stored in one of the memory cell is transmitted to the output buffer, the data stored in the next memory cell is subsequently transmitted to the output buffer.

A semiconductor memory device comprising a memory cell array includes a plurality of memory cells. The device includes: a predecoder for dividing a plurality of bits of an address signal into at least two bit strings so as to decode each bit string and output predecoded results of each bit string in parallel; a series of shift registers, each shift register being provided for a respective bit string, receiving the predecoded results of the corresponding bit string as shift data, shifting the received shift data, thereby generating and outputting predecoded signal bits; and a main decoder for decoding the predecoded signal bits output from the plurality of shift registers and selecting a memory cell in the memory cell array in accordance with the results of the decoding.

Semiconductor memory device and access method for the same

A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector means for selecting a row of the memory cell array corresponding to a row address of an input address, and column selector for selecting a plurality of columns of a memory cell array corresponding to a column address of an input address, and also selecting a plurality of columns of a memory cell array corresponding to at least one column address other than a column address of an input address. The device also includes a sense amplifier for sensing data stored in memory cells. The sense amplifier has at least two sense amplifier groups, the sense amplifier groups sensing data read from a plurality of memory cells corresponding to an input address, and data read from a plurality of memory cells corresponding to the row address of an input address and at least one other column address. The device has a page mode for rapidly switching and outputting data from a plurality of memory cells which have been read in parallel to sense amplifier in accordance with an input address.

Semiconductor memory device with dual address memory read amplifiers

A semiconductor memory device of the invention is provided with a usual access mode and a rapid access mode. The semiconductor memory device includes: a change detection circuit, provided for each of bit signals which are a part of an address signal, for detecting a change of the address signal; a timer circuit for, when the change detection circuit detects the change of the address signal, generating a signal indicating the change of the address; and an output circuit for outputting the signal generated by the timer circuit as a signal which controls a wait of access in each of the access modes.

Semiconductor memory device incorporating address change detection

A semiconductor read only memory is disclosed. The memory has a memory cell array including a plurality of memory cell groups. Each of the plurality of memory cell groups includes a plurality of memory cells. The memory has select circuit for selecting an arbitrary memory cell group from among the plurality of memory cell groups, and an address storage circuit for storing address information of an arbitrary one of the memory cell groups; and a data storage circuit for storing data to be written into the arbitrary one of the memory cell groups.

Semiconductor read only memory

A semiconductor memory including a memory cell array having a plurality of memory cells; an input buffer circuit for receiving an address signal having an amplitude at an interface level and generating at least one output signal having an amplitude at an internal logic level in accordance with said address signal, the input buffer circuit further receiving a first signal and changing the response characteristics thereof in response to the first signal; a detecting circuit for receiving the output signal and generating a detecting signal indicating whether the level of the output signal varies; and a control signal generating circuit for receiving the detecting signal and generating the first signal based on the detecting signal.

Semiconductor memory

In a mask ROM, for each of the memory cell groups, a load circuit connected to data lines for the respective memory cell group, a sense amplifier, and a switching circuit are provided. The switching circuit selectively connects one of the data lines which are simultaneously selected, to the sense amplifier. A data line for a dummy memory cell is also connected to the sense amplifier.

Semiconductor memory device with shared sense amplifiers

A semiconductor ROM includes a plurality of word lines disposed in parallel and has a plurality of units which each includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth, sub-bit lines disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. First ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line. First and second ones of the bank selecting switches are disposed in parallel between the first main bit line and the first sub-bit line, and third and fourth ones of the bank selecting switches are disposed in parallel between the second main bit line and the fourth sub-bit line. A fifth one of the bank selecting switches is disposed between the first main bit line and the third sub-bit line, and a sixth one of the bank selecting switches is disposed between the second main bit line and the second sub-bit line.

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Nara, Japan

Yasuhiro Hotta