Hitachi, Ltd.

Hitachi Denshi Kabushiki Kaisha

Yasuhiro Hirano

Mitsuo Nakajima

Masato Sugiyama

Haruki Takata

Kazuo Ishikura

Yoshizumi Eto

Takaaki Matono

Yasutaka Tsuru

Hiroshi Yoshigi

Hidehiko Jusa

Takahiko Fukinuki

Takashi Hasegawa

Seiichi Mita

Toshiyuki Kurita

Tsuguo Itagaki

Shoji Kimura

Mitunori Yamashina

Tetsuo Etoh

Takashi Kanehachi

The present invention provides a movement correction frame count transformation apparatus for carrying out frame count transformation processing on a picture signal. In the apparatus, an input picture signal (S ) of interlaced scanning is converted into a signal (S ) of sequential scanning by an IP conversion unit ( ). A movement detecting unit ( ) detects movement detection signals (MD and MD ). A block unit movement vector searching unit ( ) detects a block unit movement vector (BMV) by carrying out block matching processing. A movement vector correcting unit ( ) carries out miniblock division processing to generate a movement vector (BV) if a movement correction error is equal to or greater than a threshold value. A pixel unit movement vector generating unit ( ) generates a movement vector with a smallest error component between a frame signal of a current frame and a frame signal of an immediately preceding frame as a movement vector of a pixel. An MC interpolation frame signal generating unit ( ) generates an interpolation frame in movement correction processing carried out by a median filter in order to produce a signal (S ) of sequential scanning as a result of frame count transformation based on movement correction.

Method and device for converting number of frames of image signals

A low-cost motion-compensated picture signal scan conversion circuit ensuring high picture quality is to be provided. The circuit has a motion-adaptive first interpolation signal generator; a second motion-compensated interpolation signal generator; a motion vector detector; and a setting unit for checking the reliability of motion compensation by comparing signals from the second interpolation signal generator with signals on interlaced scanning lines, and setting the selection of signals from the first and second interpolation signal generators, wherein interlaced scanned signals are converted into progressive scanned signals by setting the threshold so that the threshold become smaller with an increase in the number of re-searched blocks in the detection of motion vectors.

Circuit for scan conversion of picture signal using motion compensation

In order to carry out format conversion or scaling processing of picture signal by a memory having a small capacity, picture signals of interlace scanning are converted into picture signals of progressive scanning by interpolation by using an IP convertor 1 and a multiple scan convertor 3, a scaling processing of expansion and compression in the horizontal direction is firstly performed by using a horizontal scaling unit 5, processing of expansion, compression, frame rate conversion, synchronization and the like are secondly performed by using a vertical scaling unit 6 and commonly using memories used in scaling processing in the vertical direction and finally, color space conversion or inverse gamma processing is performed by using a picture quality improving unit 8 thereby converting the picture signals into picture signals S6 having a predetermined format.

Method and circuit for signal processing of format conversion of picture

A controlling apparatus for an induction motor for controlling the induction motor in high efficiency having a converter for supplying an electric power to the induction motor, a rotational speed detector of the induction motor, a controlling means of the converter for holding a torque of the induction motor constant while the rotational speed of the induction motor is lower than a base rotational speed and to decrease a secondary magnetic flux of the induction motor according to the rotational speed while the rotational speed of the induction motor is over the base rotational speed, and a means for varying the secondary magnetic flux according to a terminal voltage of the induction motor so as to hold the terminal voltage a predetermined constant voltage while the rotational speed of the induction motor is higher than the predetermined speed.

Controlling apparatus for induction motor

A television signal transmission system having an improved receiver which system is capable of transmitting a wide-band television video signal in a frequency band narrower than the frequency band of the television video signal is a multiplex video signal and the receiver reproduces a luminance signal and color signal from the multiplexed video signal. The receiver includes a motion detector for detecting motion information of a picture from the multiplex video signal and a separator for separating signals in response to the detected motion information to thereby form a picture of high quality utilizing the motion information.

High resolution color television signal transmission system and receiver

In a color television signal processing system for converting a scanning signal sequentially scanned in the transmitting side into an interlace-scanned television signal in order to obtain a high-quality color television picture, said system is arranged to detect information related to picture motion and that concerning to a spatio-temporal frequency characteristic and to control a characteristic of a spatio-temporal filter for transmitting a luminance signal on the basis of this information and to transmit the signal expressing the information multiplied with the color television signal.

Television signal processing system

In order to prevent deterioration of a reproduced picture quality due to lack of the clock signals, a video signal decoding circuit produces quasi-code signals when the lack of clock signal is detected.

Video signal decoding circuit

Magnetic recording and reproducing method and apparatus for digital signals. An input binary digital signal is converted into an intermediate signal series by a precoder having a delay circuit for two-time slot delay and a modulo-2 adder. The intermediate signal series is branched to two paths. One signal on one path is delayed by one time slot and subtracted from the other signal on the other path to produce a recording signal to be recorded on a recording medium. A signal reproduced from the recording medium is branched to two paths. One signal on one path is delayed by one time slot and added to the other signal on the other path. The added signal is decoded to produce a binary signal which corresponds to the input binary digital signal.

Growing community of inventors

Hachioji, Japan

Yasuhiro Hirano