Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Nippon Suisan Kaisha, Ltd.

Toppan Forms Co., Ltd.

Electric Industry Co., Ltd.

Yasuhiro Fukuda

Hirokazu Hayashi

Toshikazu Kuroda

Katsuhiro Kato

Hiroshi Onoda

Yusuke Harada

Takaaki Okita

Shooji Kitazawa

Jiro Takeo

Makiko Nakamura

Shuji Jinno

Naomi Ohtsuka

Junichiro Hata

Shinya Yamashita

Hiroyuki Onuki

Yasuyo Kogure

Yasuyuki Tatara

Akira Yamazaki

Hideo Shimizu

Minoru Saito

Norio Hirashita

Noboru Egawa

Yoshiaki Ide

Mitsuhiro Matsuo

Takeshi Yamakami

Tsuyoshi Goto

Yoshiaki Katakura

Itaru Shioya

Yukihiko Isetani

Masayuki Kobayakawa

Tetsuhiko Sugahara

Hideki Nikaido

Fumitaka Yokoyama

Takaaki Okada

Shinnichi Fukuzako

Yosuke Tanaka

Fumihiro Hanazawa

Ikuo Suganuma

Taeko Kousaka

This invention provides a feed for fish farming which is excellent in terms of stability of feed supply and feed shelf life and which has excellent feed intake and feed efficiency. The feed for fish farming has an outer layer and an inner layer, characterized in that a composition constituting the outer layer has a breaking stress of 5&#xd7;10to 1&#xd7;10N/m, a cohesiveness (30%) of 0.4 to 1.0, and a breaking strain of 30 to 80%. The feed for fish farming is characterized by having an outer layer constructed from a heat-induced gel which comprises a protein and/or a starch, and an inner layer comprising a composition which contains nutrient ingredients having fish meal and an oil as essential ingredients.

Feed for fish farming

A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer.

Semiconductor device with ESD protection function and ESD protection circuit

Sheet-like audio information recording/reproducing means capable of recording/reproducing audio information is sandwiched between two support sheets from front and back only in part of the area thereof and these two support sheets are further sandwiched between two surface sheets and the support sheets and surface sheets are bonded together.

Audio message transfer sheet and manufacturing method thereof, and power supply circuit

A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Semiconductor device having fuse and protection circuit

A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is connected between the second terminal of the fuse and the gate of the transistor. The protection capacitor supplies the threshold voltage to the transistor where the fuse supplies the fixed voltage to the protection capacitor.

Semiconductor device having fuse with protection capacitor

A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

Load driving device

An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. The first capacitive element restricts a current from flowing from the second terminal of the thyristor rectifier circuit to the internal source voltage, even when the external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. This prevents the thyristor rectifier circuit from malfunctioning and turning on.

Electro-static discharge protection circuit and semiconductor device having the same

An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.

An electrostatic breakdown preventing circuit has first and second conductive lines, a diode, a power clamp circuit and first and second capacitors. The first and second conductive lines are connected to a first potential source and a second potential source, respectively. The internal circuit is connected between the first and second conductive lines. The internal circuit operates in response to an input signal. The diode is connected in a forward direction between an input terminal and the second conductive line. The first capacitor is connected between the node and the first conductive line. The second capacitor is connected between the node and the second power conductive line. The capacitances of the first and second capacitors are set in such a manner that the transistor is brought to an OFF state upon a normal operation and brought to an ON state upon the input of an electrostatic surge.

Electrostatic breakdown preventing circuit for semiconductor device

The present invention offers a tracheal smooth muscle relaxant containing the compound represented by the following formula (1) or pharmacologically acceptable salt thereof as an effective ingredient.

Tracheal smooth muscle relaxants

A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is-formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers. If the same metal is used for the metal layer and the nitride layer, the same vacuum chamber may be used to apply both layers, by replacing an inert gas atmosphere used during metal layer deposition by a nitrogen gas atmosphere for use during the nitride layer deposition.

Semiconductor device having multi-layered metalization and method of manufacturing the same

When a semiconductor integrated device is in an inactive state without being supplied with electric power, depletion type NMOS transistors act as resistors whereby a signal line connected to an input pad is electrically connected to the sources of input transistors via the NMOS transistors. In this situation, if an electrostatic surge is applied to the input pad, the surge is released to a voltage supply line. This ensures that the semiconductor integrated device is prevented from being damaged by the electrostatic surge. When electric power is supplied to the semiconductor integrated device and it becomes active, the NMOS transistors come to behave as insulating elements and thus these NMOS transistors have no adverse effects on the normal operation of the semiconductor integrated device.

Electrostatic damage protection circuit and dynamic random access memory

Tracheal smooth muscle relaxant

Growing community of inventors

Tokyo, Japan

Yasuhiro Fukuda