Fujitsu Corporation

Other

Fujitsu Semiconductor Limited

Fujitsu Vlsi Limited

Yasuhiro Fujii

Masao Nakano

Yasurou Matsuzaki

Fuminori Yumitori

Yoshihiro Takemae

Junji Ogawa

Tomio Nakano

Nobuhiro Tazoe

Takeo Tatematsu

Sadakazu Masuda

Kenichi Ide

Takashi Horii

Shigeki Narushima

Yasushi Dodo

Shuichi Yamashina

Hiroyoshi Tomita

Atsushi Hatakeyama

Toshiya Uchida

Kenichi Kawasaki

Kazuyuki Sato

Hirohiko Mochizuki

Satoshi Murata

Yukinori Kodama

Makoto Yanagisawa

Yoichi Motoyashiki

Shozo Ikemune

Norihisa Tsuge, Deceased

Masaaki Yamamoto

Masataka Mizukoshi

Shoichiro Kawashima

Kimiaki Sato

Kazuaki Takai

Keizo Morita

Shinnosuke Kamata

Nobutaka Taniguchi

Hisashi Honjou

Isao Imai

Hidehiko Akasaki

Toru Minote

Hisashi Sato

Norihisa Tsuge

Akira Sugiura

Shinji Okazaki

Toyonobu Yamada

Hiroshi Sekine

Hajime Ishii

Masami Matsuoka

Kinichi Higuchi

Takumasa Terauchi

Toshihiko Obata

Tomoharu Oka

Mitsuhiro Ogai

Hirokazu Yamazaki

Kazuaki Yamane

Sachie Tsuge

Itaru Tsuge

A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

Semiconductor device and system

A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

Semiconductor device, method of testing the semiconductor device, and semiconductor integrated circuit

A data transfer memory comprises a plurality of memory devices having the function of transferring data on a system bus or a plurality of memory modules each having the plurality of memory devices. Herein, a memory module buffer in each memory device or memory module and a controller chip located on the system bus include a return clock input/output circuit for inputting or outputting a return clock generated using a clock output from a data processing unit such as a CPU, and an output activation circuit for activating output of data from the memory device in response to a data output enabling signal generated by using the return clock output from the return clock input/output circuit.

Data transfer memory having the function of transferring data on a system bus

A material to be shaped is reduced and formed by bringing dies with convex forming surfaces, when viewed from the side of the transfer line of the material close to the transfer line from above and below the material in synchronism with each other, while giving the dies a swinging motion in such a manner that the portions of the forming surfaces of the dies, in contact with the material are transferred from the upstream to the downstream side in the direction of the transfer line.

Plate reduction press apparatus and methods

A high-quality hot rolled steel sheet is manufactured with a high production efficiency and a low cost, from a long, hot slab, using a combination of continuous casting facilities and a plate reduction press machine.

Apparatus and methods for manufacturing hot rolled steel sheets

The die changing apparatus for a plate reduction press machine, comprises an upper die support holder,and a lower die support holder,that are arranged vertically on opposite sides of a transfer line, and support holder guide rails,installed on the upper die support holder and extending substantially horizontally in the lateral direction of the transfer line, and an upper die,and a lower die,are mounted on the upper and lower die support holders, respectively using the rollers onto the dies, fixing devices,that fix the upper and lower dies on the upper and lower die support holders, respectively, die fastening members,which are placed on each side of the upper and lower dies, opposite each other in such a manner that they can be fastened to both dies, and a die changing mechanism that can move one of the die fastening members in a direction perpendicular to the transfer line.

Apparatus and method for changing dies

The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal. The delay control circuit generates a single delay control signal, which changes by a minimum delay quantity unit a delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal, which changes by a binary unit a delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit. A lock-on state can be achieved in a short time, and stable operation is possible.

DLL circuit

A switch 17 for short-circuiting is connected between the outputs of circuits 15 and 16 each of which outputs a pair of complementary signals .0.S1 and .0.R1. The circuits 15 and 16, and the switch 17 are controlled by a changeover control circuit 18 in response to an input signal .0.A1. To effectively utilizes electric charge which has become unnecessary on a complementary signal line pair, the circuit 18 comprises an edge detecting circuit for providing a pulse to the switch 17 to make it on in response to the edge of the signal .0.A1, and a state control circuit for making the outputs of the circuits 15 and 16 in a high impedance state while the switch 17 being on, and for making the logic states of the signals .0.S1 and .0.R1 completely transit in response to disappearance of the pulse while the switch 17 being off.

Semiconductor device utilizing unnecessary electric charge on

A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.

Semiconductor device having timing-stabilization circuit and method of

A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Semiconductor wafer testing method with probe pin contact

In the present invention, when a phase comparison circuit, which compares the phase of a reference clock divided by a frequency divider that frequency divides a supplied clock, to that of a variable clock, detects the phase-matching of the two clocks, it generates a phase synchronization detection signal, and this phase synchronization detection signal increases the frequency division ratio of a frequency divider, lowering the frequency of operation of the phase comparator. The present invention is further characterized in that, at reset, when an inactive state becomes an active state, the time required to phase synchronize both clocks is shortened by resetting the above-described phase synchronization detection signal, thereby setting the frequency division ratio of the frequency divider to its original low state, and the frequency of operation of the phase comparator to its original high state. In accordance with the above-described invention, when phase synchronization is detected in an active state, the frequency division ratio of the frequency divider is increased, and the frequency of operation of the phase comparator is lowered, thus curbing power consumption. Then, at reset, this phase synchronization detection signal is reset, thus returning the frequency division ratio of the frequency divider to its original low state, and raising the frequency of phase comparator operation.

Integrated circuit device

A semiconductor memory device according to this invention has a hierarchical bit line structure where a plurality of local bit lines are provided in parallel to each global bit line and some of the local bit lines in the column direction are connected to the global bit line. Such memory device further has an open bit line structure where global bit lines are provided on both sides of sense amplifiers, and has bit-line transfer circuits, provided between the global bit lines and the sense amplifiers, for isolating the global bit lines from the sense amplifiers when the sense amplifiers are activated. The use of the hierarchical bit line structure in combination with the open bit line structure enhances the layout efficiency of memory cells, and the provision of the bit-line transfer circuits overcomes a problem of erroneous data reading which would otherwise be caused by bit line noise inherent to the open bit line structure.

Semiconductor memory device

A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.

Semiconductor memory with hierarchical bit lines

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Kawasaki, Japan

Yasuhiro Fujii