Denso Corporation

Yasuhiro Ebihara

Yuichi Takeuchi

Yusuke Yamashita

Masahiro Sugimoto

Shuhei Mitani

Hidekazu Tsuchida

Sachiko Aoi

Hidefumi Takaya

Tatsuji Nagaoka

Isaho Kamata

Shinichiro Miyahara

Hiroyuki Kondo

Shoichi Onda

Tadashi Misumi

Aiko Kaji

Takashi Kanemura

Takeshi Okamoto

Yukihiro Watanabe

Ryohei Tanuma

A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.

Manufacturing method of semiconductor device including semiconductor element of inversion type

A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

Semiconductor device and method for manufacturing the same

Semiconductor device including saturation current suppression layer

A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

Semiconductor device and method for manufacturing same

A silicon carbide semiconductor device includes: a substrate; a first impurity region on the substrate; a base region on the first impurity region; a second impurity region in the base region; a trench gate structure including a gate insulation film and a gate electrode in a trench; a first electrode connected to the second impurity region and the base region; a second electrode on a rear surface of the substrate; a first current dispersion layer between the first impurity region and the base region; a plurality of first deep layers in the second current dispersion layer; a second current dispersion layer between the first current dispersion layer and the base region; and a second deep layer between the first current dispersion layer and the base region apart from the trench.

Silicon carbide semiconductor device and method for manufacturing same

A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0&#xb0; and within 40&#xb0; is set to 300 dislocations/cmor less. Furthermore, a density of the threading dislocations having the angles larger than 40&#xb0; is set to 30 dislocations/cmor less.

Silicon carbide single crystal, silicon carbide single crystal wafer, silicon carbide single crystal epitaxial wafer, and electronic device

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Kariya, Japan

Yasuhiro Ebihara