Panasonic Corporation

Socionext Inc.

Matsushita Electric Industrial Co., Ltd.

Yasuhiro Agata

Masanori Shirahama

Toshiaki Kawasaki

Yasue Yamamoto

Shinichi Sumi

Ryuji Nishihara

Hirohito Kikukawa

Yoshinobu Yamagami

Akira Masuo

Yutaka Terada

Tsuyoshi Koike

Kenji Misumi

Hidenari Kanehara

Norihiko Sumitani

Osamu Ichikawa

Katsuya Arai

Mitsuaki Hayashi

Wataru Abe

Masakazu Kurata

Tomohiro Kurozumi

Toshihiro Kougami

Noriaki Narumi

Shintaro Nagai

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

FINFET based driver circuit

Finfet based driver circuit

A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Semiconductor memory device with a selection transistor having same shape and size as a memory cell transistor

A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Semiconductor device

A system LSI () having a logic circuit () and a plurality of SRAM macros () includes a power supply circuit () configured to receive a voltage (VDDP) supplied from the outside of the system LSI (), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell () of each of the plurality of SRAM macros () is supplied with the voltage (VDDM) generated by the power supply circuit (), and an SRAM logic circuit () of each of the plurality of SRAM macros () is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit () is supplied with the voltage (VDD) from the outside.

Semiconductor integrated circuit

A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.

Semiconductor memory device

In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

Nonvolatile semiconductor memory device

An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Electronic equipment system and semiconductor integrated circuit controller

A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.

A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

System LSI

A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.

Electric fuse circuit available as one time programmable memory

A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.

Electrical fuse circuit

The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Growing community of inventors

Osaka, Japan

Yasuhiro Agata