Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Zentel Japan Corporation

Yasuhiko Tsukikawa

Takashi Itou

Mikio Asakura

Susumu Tanida

Takashi Kubo

Koji Tanaka

Takeshi Hamamoto

Kenichi Yasuda

Kyoji Yamasaki

Masaru Haraguchi

Takashi Ito

Hironori Iga

Yukiko Maruyama

Goro Hayakawa

Tsukasa Ooishi

Kiyohiro Furutani

Masaki Tsukude

Shinji Tanaka

Hiroshi Miyamoto

Takeo Miki

Takayuki Miyamoto

Yayoi Nakamura

Katsuhiro Suma

Shigeru Kikuda

Mikio Sakurai

Kengo Aritomi

Masaya Nakano

Jun Nakai

Takahiko Fukiage

Hisao Kobashi

Masaki Shimoda

A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Semiconductor memory device

A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor

A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Semiconductor device and level conversion circuit

Independent power supply systems are provided for a peripheral circuit other than a column decoder, an array-relevant circuit, and a column decoder respectively, so that a peripheral power supply voltage, an array power supply voltage, and a column decoder power supply voltage generated independently of each other are supplied to the peripheral circuit, the array-relevant circuit, and the column decoder as an operating power supply voltage, respectively. Preferably, the column decoder power supply voltage during normal operation is set as an intermediate voltage between the peripheral power supply voltage and the array power supply voltage. Thus, an array configuration suitable for driving a transistor with a low voltage in order to achieve lower power consumption can be obtained.

Semiconductor memory device driven with low voltage

Each cell unit has a cell plate electrically isolated from the cell plates in the other cell units.

Semiconductor memory device having dummy word line

A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.

Semiconductor device with reduced terminal input capacitance

Each of twin-cell units each formed of two DRAM cells has a cell plate electrically isolated from the cell plates in the other twin-cell units. Thereby, voltages on two storage nodes storing mutually complementary data in the same twin-cell unit change similarly to each other owing to capacitive coupling.

Semiconductor memory device having twin-cell units

A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2&#xb7;F&#xb7;3&#xb7;F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.

Semiconductor memory device with memory cells arranged in high density

There is provided a semiconductor memory device including eight memory blocks to , first data bus , and second data bus . The eight memory blocks are arranged at respective eight of the total nine areas to defined in a three rows by three columns matrix except for a center area . A first data bus linearly extends between memory blocks in the first and second row of the matrix. A second data bus linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.

Semiconductor memory device with shortened connection length among memory block, data buffer and data bus

In a semiconductor memory circuit including a memory cell array and first and second sense amplifier circuits provided at opposite sides of the memory cell array, respectively and having a plurality of first sense amplifiers and a plurality of second sense amplifiers, respectively, a first bit line and sense amplifier interconnecting circuit, a first bit line equalizing circuit and a first short-circuiting transistor circuit are provided between the memory cell array and the first sense amplifier circuit, while a second bit line and sense amplifier interconnecting circuit, a second bit line equalizing circuit and a second short-circuiting transistor circuit are provided between the memory cell array and the second sense amplifier circuit. Each of the first and second sense amplifiers is formed by a first transistor having a first gate insulation film, while each of the first and second bit line and sense amplifier interconnecting circuits, the first and second bit line equalizing circuits and the first and second short-circuiting transistor circuits is formed by a second transistor having a second gate insulation film thicker than the first gate insulation film.

Semiconductor memory circuit having normal operation mode and burn-in test mode

A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.

Configuration for generating a clock including a delay circuit and method thereof

There is provided with A flip-flop circuit for setting one of first and second storage nodes at one of first and second potential levels and the other storage node at the other potential level in accordance with stored data, and a switch circuit electrically coupling an internal node electrically coupled to a bit line to a first potential in accordance with the potential level of the one storage node.

Semiconductor memory device having nonvolatile memory cell of high operating stability

This three-valued inverter includes first and second P-channel MOS transistors connected in series between a line of a first power supply potential and an output node, and each having a gate receiving a first signal; third and fourth P-channel MOS transistors connected in series between a line of a second power supply potential and the output node, and each having a gate receiving a second signal; and an N-channel MOS transistor connected between the output node and a line of a ground potential, and having a gate receiving a third signal. Back gates of the first and third P-channel MOS transistors are applied with the first power supply potential and the second power supply potential, respectively, and back gates of the second and fourth P-channel MOS transistors are both connected to the output node. Therefore, even in a power-up period or the like, no latch-up occurs.

Multi-valued logical circuit with less latch-up

In response to an output data width switching mode signal, a predecoder zone&plus;selector zone outputs selection signals SEL to SEL and WORDA to WORDC to a preamplifier&plus;write driver zone. The preamplifier&plus;write driver zone can switch connection between global I/O lines GIO< > to GIO< > and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

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Hyogo, Japan

Yasuhiko Tsukikawa