Micron Technology Incorporated

Yasuhiko Tanuma

Takashi Ishihara

Toshinao Ishii

Takayori Hamada

An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Apparatus comprising antifuse cells

Semiconductor devices and systems are disclosed. A semiconductor device includes a redistribution layer including a first polygonal structure for conveying a first power signal and including a first cutout region. The semiconductor device further includes a second polygonal structure for conveying a second power signal. Further, the semiconductor device includes an island polygon for conveying a third power signal and positioned within the first cutout region, wherein the island polygon does not touch the first polygonal structure.

Routing for power signals including a redistribution layer

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

Apparatuses and methods for semiconductor circuit layout

Semiconductor devices and systems include semiconductor devices with first signal traces conveying a first power signal, second signal traces conveying a second power signal, and third signal traces conveying a third power signal. Each of the power signals are connected on a redistribution layer, a first wiring layer, and first-layer contacts. At least one of the first signal traces on the redistribution layer includes a cutout region and the third signal traces include a bypass structure on the redistribution layer and within the cutout region. The bypass structure conveys the third power signal on the redistribution layer around the first-layer contacts coupled to the first signal traces on the redistribution layer.

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Tokyo, Japan

Yasuhiko Tanuma