Ntt Electronics Corporation

Yasuhiko Takeo

Masaki Hirose

Masatoshi Tobayashi

Yukio Akazawa

A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminalof a multiplier circuitapproaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Growing community of inventors

Tokyo, Japan

Yasuhiko Takeo