Semiconductor Energy Laboratory Co., Ltd.

Other

Yasuhiko Takemura

Shunpei Yamazaki

Hongyong Zhang

Toru Takayama

Hideki Uochi

Naoaki Yamaguchi

Hisashi Ohtani

Toshimitsu Konuma

Akira Mase

Hideto Ohnuma

Masaaki Hiroki

Hideomi Suzawa

Akiharu Miyanaga

Satoshi Teramoto

Jun Koyama

Hiroki Adachi

Naoto Kusumoto

Akira Takenouchi

Takeshi Fukunaga

Akira Sugawara

Yukiko Uehara

Atsunori Suzuki

Yasuyuki Arai

Kunihiko Suzuki

Setsuo Nakajima

Mutsuo Yamamoto

Satoshi Seo

Nobuharu Ohsawa

Hideko Inoue

Satoko Shitagaki

Hiromichi Godo

Harue Osaka

Hiroshi Kadoma

Junichi Takeyama

Hideki Nemoto

Yoshiyuki Kurokawa

Toshiji Hamatani

Mitsunori Sakama

Takeshi Fukada

Hiroshi Uehara

Shunepi Yamazaki

Kiyoshi Kato

Yoshiharu Hirakata

Tetsuhiro Tanaka

Takayuki Inoue

Yuji Kawasaki

Norihiko Seo

Sunpei Yamazaki

Yasumasa Yamane

Hiroyuki Shimada

Toshihiko Takeuchi

Minoru Miyazaki

Akane Murakami

Tomohiko Sato

Masamitsu Hiroki

Shigefumi Sakai

Hognyong Zhang

Hiroyuki Miyake

Koichiro Tanaka

Takayuki Ikeda

Masahiko Hayakawa

Mitsuhiro Ichijo

Yuki Okamoto

Yoshitaka Yamamoto

Tamae Moriwaka

Toshiya Endo

Kuniharu Nomoto

Eiji Sato

Hiroatsu Todoriki

Itaru Koyama

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Semiconductor device comprising wiring layer over driver circuit

A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more.

Light-emitting device

A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.

Semiconductor device and method for manufacturing semiconductor device

Semiconductor device comprising first and second conductors

A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.

Semiconductor device and method of driving semiconductor device

Semiconductor device including side surface conductor contact

Semiconductor memory device comprising memory cell over driver

It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.

Semiconductor device

Provided is a method for measuring a current that a component of a matrix device can supply. A device including components (pixels) arranged in a matrix, first wirings, and second wirings and third wirings which cross the first wirings is used. Each component includes a potential supply circuit, a transistor, and a capacitor. The device is designed as follows: at a point in time, one electrode of the capacitor has a potential equal to that of a gate of the transistor, the other electrode of the capacitor has a potential equal to that of the second wiring, one of a source and a drain of the transistor has a potential equal to that of the first wiring, and the other of the source and the drain of the transistor has a potential equal to that of the third wiring; and the potential of the second wiring and the potential of the third wiring in the case where each component supplies the first wiring with a current in a given direction are different from the potential of the second wiring and the potential of the third wiring in the case where each component supplies the first wiring with a current in the opposite direction.

Measurement method for a device, matrix device, and method for driving matrix device

Semiconductor memory device including multilayer wiring layer

Growing community of inventors

Kanagawa, Japan

Yasuhiko Takemura