Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Yasuhiko Onishi

Susumu Iwamoto

Takahiro Sato

Tatsuhiko Fujihira

Katsunori Ueno

Tatsuji Nagaoka

Takahiro Tamura

Yasushi Niimura

Mutsumi Kitamura

Takeyoshi Nishimura

Akio Sugi

Masanori Inoue

Kenji Kunihara

Dawei Cao

Hitoshi Abe

Manabu Takei

Takashi Kobayashi

Masahito Otsuki

Ryu Saito

A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an nregion with a lower impurity concentration than the n-type drift region.

Method for manufacturing a semiconductor device having a super junction MOSFET

A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an nregion with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation.

Semiconductor device including a super junction MOSFET

A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

Semiconductor apparatus

A drain drift portion is a first parallel p-n structure, largely corresponding to a portion directly below a p-type base region forming an active region, formed by first n-type regions and first p-type regions being alternately and repeatedly joined. The periphery of the drain drift portion is an edge termination region formed of a second parallel p-n structure aligned contiguously to the first parallel p-n structure and formed by second n-type regions and second p-type regions being alternately and repeatedly joined. An n-type buffer layer is provided between the first and second parallel p-n structures and an ntype drain layer. A ptype drain region is selectively provided inside the ntype drain layer in the edge termination region, penetrating the ntype drain layer in the depth direction.

Semiconductor element including active region, low resistance layer and vertical drift portion

A super junction MOSFET is disclosed. The super junction MOSFET includes a plurality of mutually parallel pn junctions extending in a vertical direction on a first principal surface of an n-type semiconductor substrate; a parallel pn layer in which n-type drift regions and p-type partition regions, each sandwiched between the adjacent pn junctions, are disposed alternately in contact with each other; and an MOS gate structure on the first principal surface side of the parallel pn layer, wherein an n-type first buffer layer and second buffer layer are in contact in that order on the opposite principal surface side, and the impurity concentration of the first buffer layer is a concentration that is equal to or less than the same level as that of the impurity concentration of the n-type drift region.

Super junction MOSFET, method of manufacturing the same, and complex semiconductor device

A superjunction semiconductor device is disclosed in which the tradeoff relationship between on-resistance and breakdown voltage is improved greatly so that reverse recovery capability is improved. A drain drift portion substantially corresponds to a portion just under p-base regions serving as an active region and forms a first parallel pn structure in which a first n-type region and a first p-type region are joined to each other alternately and repeatedly. A drain drift portion is surrounded by edge termination region including a second parallel pn structure. Edge termination region is formed such that second n-type and p-type regions oriented consecutively to the first parallel pn structure of the drain drift portion are joined to each other alternately and repeatedly. N-buffer layer is provided between first and second parallel pn structures and n+ drain layer. P-buffer layer is provided selectively inside n-buffer layer in edge termination region.

Semiconductor device

A superjunction semiconductor device is disclosed in which the trade-off relationship between breakdown voltage characteristics and voltage drop characteristics is considerably improved, and it is possible to greatly improve the charge resistance of an element peripheral portion and long-term breakdown voltage reliability. It includes parallel pn layers of n-type drift regions and p-type partition regions in superjunction structure. PN layers are depleted when off-state voltage is applied. Repeating pitch of the second parallel pn layer in a ring-like element peripheral portion encircling the element active portion is smaller than repeating pitch of the first parallel pn layer in the element active portion. Element peripheral portion includes low concentration n-type region on the surface of the second parallel pn layer. The depth of p-type partition region of an outer peripheral portion in the element peripheral portion is smaller than the depth of p-type partition region of an inner peripheral portion.

Superjunction semiconductor device

A parallel p-n layer () is provided as a drift layer between an active portion and an ndrain region (). The parallel p-n layer () is formed by an n-type region () and a p-type region () being repeatedly alternately joined. An n-type high concentration region () is provided on a first main surface side of the n-type region (). The n-type high concentration region () has an impurity concentration higher than that of an n-type low concentration region () provided on a second main surface side of the n-type region (). The n-type high concentration region () has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (). Also, the n-type high concentration region () has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region () adjacent to the p-type region ().

Superjunction semiconductor device with reduced switching loss

A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An nsurface area is disposed between the second parallel p-n layer and a first principal face. Two or more p-type guard ring areas are disposed so as to be separate from each other on the first principal face side of the nsurface area. First field plate electrodes and second field plate electrodes are electrically connected to p-type guard ring areas. Second field plate electrodes cover the first field plate electrodes adjacent to each other so as to cover the first principal face between the first field plate electrodes through a second insulating film.

A super-junction semiconductor device includes a drift layer including an alternating-conductivity-type layer that includes n-type region and p-type region arranged alternately in parallel to the first major surface of an n-type substrate. These alternating regions extend deep in a direction perpendicular to the first major surface. The first major surface includes a main device region with a gate electrode and a main source electrode and sensing device region with a gate electrode and a sensing source electrode. There is a common drain electrode on the second major surface of the substrate. There is a separation region between the main device region and the sensing device region. It includes an n-type region and p-type regions in the n-type region. The p-type regions are in an electrically floating state in the directions parallel and perpendicular to the first alternating-conductivity-type layer.

Super-junction semiconductor device

Semiconductor regions are alternately arranged in a parallel pn layer in which an n-type region and a p-type region are alternately arranged parallel to the main surface of a semiconductor substrate. Pitch between n drift region and p partition region of a second parallel pn layer in an edge termination region is two thirds of pitch between n drift region and p partition region of a first parallel pn layer in an active region. At boundaries between main SJ cells and fine SJ cells at four corners of the semiconductor substrate having rectangular shape in plan view, ends of two pitches of main SJ cells face the ends of three pitches of fine SJ cells. In this way, it is possible to reduce the influence of a process variation and thus reduce mutual diffusion between n drift region and p partition region of the fine SJ cell.

High breakdown voltage semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.

Semiconductor device with superjunction structure

A semiconductor device is provided with a peripheral region that has a narrow width and exhibits good electric field relaxation and high robustness against induced charges. The device has an active region for main current flow and a peripheral region surrounding the active region on a principal surface of a semiconductor substrate of a first conductivity type. The peripheral region has a guard ring of a second conductivity type composed of straight sections and curved sections connecting the straight sections formed in a region of the principal surface surrounding the active region, and a pair of polysilicon field plates in a ring shape formed separately on inner and outer circumferential sides of the guard ring. The surface of the guard ring and the pair of polysilicon field plates of the inner circumferential side and the outer circumferential side are electrically connected with a metal film in the curved section.

Semiconductor device and a method of manufacturing the same

A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge.

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Nagano, Japan

Yasuhiko Onishi