Yamaha Corporation

Yamaha Hatsudoki Kabushiki Kaisha

Yasuhiko Matsumoto

Junichi Inami

Yasushi Kishi

Hattori Atsuo

A magnesium alloy part includes a part body composed of a magnesium alloy containing aluminum; a paint film at least partially covering the part body; and a magnesium fluoride layer provided immediately under the paint film. The magnesium alloy has an aluminum content of about 6.5 weight % or less.

Magnesium alloy part and production method thereof

A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.

Method of manufacturing a semiconductor device with flattened

A multi-layered wiring structure, having a first level metal wiring layer and a second level metal wiring layer, is formed on a semiconductor substrate. A first level interlayer insulating film which has an undulation caused by the first level metal wiring layer, a second level metal wiring layer which also has an uneven surface, and a second level interlayer insulating layer are consecutively deposited on the semiconductor substrate. A reflection preventing film (TiN) of 80 nm or more thickness is deposited over the second level interlayer insulating film, and a resist layer is coated on the reflection preventing film. Then, an ultra-violet ray is irradiated through a patterning mask to make an opening corresponding to a contact hole. The reflection preventing film constrains a multi-reflection of the ultra-violet ray. Thus, an accuracy of the patterning of the contact hole is improved.

Method of forming multilayered wiring

A process of fabricating a multi-level wiring structure starts with preparation of a semiconductor substrate covered with a lower insulating film, and comprises the steps of forming lower-level wiring strips on the lower insulating film, covering the lower-level wiring strips and exposed portions of the lower insulating film with a first intermediate insulating film, coating the entire surface with an organic glass film, removing the organic film except for pieces of the organic glass film in valleys between the lower-level wiring strips, coating the entire surface with an inorganic glass film, removing the inorganic glass film except for pieces of the inorganic glass film on the pieces of the organic glass film, covering the entire surface with a second intermediate insulating film, and forming upper-level wiring strips on the intermediate insulating film, wherein the pieces of the inorganic glass film prevent the upper-level wiring strips from corrosion due to water vapor produced from the pieces of the organic glass film.

Growing community of inventors

Shizuoka, Japan

Yasuhiko Matsumoto