Fujitsu Corporation

Fujitsu Vlsi Limited

Fujitsu Semiconductor Limited

Yasuhiko Maki

Toshiyuki Uetake

Osamu Nomura

Hiroshi Shimizu

Yoshinori Okajima

Isao Fukushi

Hiroshi Kagiwata

Koji Shimosako

Fujitsu Limited

Takako Kagiwata

A semiconductor memory device comprising a regular cell array that includes a regular memory cell to which one of a first power supply voltage and a second power supply voltage is supplied and to which a third power supply voltage is supplied, a redundant cell array that includes a redundant memory cell to which one of the first power supply voltage and the second power supply voltage is supplied and to which the third power supply voltage is supplied, and a power supply control circuit that controls supply of the first power supply voltage and the second power supply voltage to the regular cell array and the redundant cell array, wherein a difference between the second power supply voltage and the third power supply voltage is smaller than a difference between the first power supply voltage and the third power supply voltage.

Semiconductor memory device and control method thereof

A semiconductor memory including a sense amplifier circuit for reading the data stored in memory cells and particularly to a semiconductor memory including a self-timing circuit for improving margin for reading data by controlling activation timing of the sense amplifier drive signal in accordance with characteristics of internal memory cells.

Semiconductor memory including self-timing circuit

Each memory cell has a pair of inverters whose inputs and outputs are connected to each other and holds complementary data respectively in storage nodes which are outputs of the inverters. In a write operation during which the complementary data are written to the storage nodes respectively, the power control circuit sets a power supply voltage of the inverter having the storage node to which low level is written lower than a power supply voltage of the inverter having the storage node to which high level is written. Since power supply capability to the inverter having the storage node to which the low level is written lowers, the voltage of the storage node easily changes to the low level. That is, a write margin of a memory cell can be improved.

Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines

An integrated circuit device of the invention, has a memory macro which during normal operation latches an input address in response to a control pulse and generates data output corresponding to the input address, and a test control circuitwhich during testing performs memory macro characteristic tests. A ring oscillator is configured by connecting a prescribed number of stages including one or more memory macro units, having a memory macro and a pulse generation circuit which during testing generates a control pulse for tests in response to an input pulse, and the test control circuit measures the oscillation frequency or period of the ring oscillator.

Integrated circuit device having a test circuit to measure AC characteristics of internal memory macro

In case that data are written in a flip-flop circuit by inverting the voltage to be supplied to a pair of write bit lines, the peak of the current waveform flowing in the pair of write bit lines is to be made gentler, whereby reduced power source noise and low power consumption should be achieved. To this end in a semiconductor device wherein flip-flop circuit for holding data, a memory cell including a transfer gate, a pair of write bit lines for writing data in the memory cell, are provided, in case that data are written in the flip-flop circuit by inverting the voltage to be supplied to the pair of write bit lines, the slew rate of the voltage to be supplied to the pair of write bit lines is made equal to predetermined value or less.

Semiconductor device

Included are first and second invertersL,R, a first selection transistor Ncontrolling a connection of an output terminal of the first inverterL to a bit line, and a second selection transistor Ncontrolling a connection of an output terminal of the second inverterR to a bit line, wherein the first inverterL having a first load transistor Pand a first drive transistor Nand the second inverterR having a second load transistor Pand a second drive transistor N, function as a memory cell, and a ratio of a driving current quantity that can be outputted in an ON-state of the first drive transistor Nto a driving current quantity that can be outputted in an ON-state of the first selection transistor N, is larger than a first predetermined value.

Semiconductor memory device

A semiconductor memory device includes a data access path for accessing a memory cell, a signal drive circuit which drives a signal on said data access path, a dummy path that emulates said data access path, and a dummy drive circuit which emulates said signal drive circuit, wherein said dummy path has a smaller load than said data access path, and said dummy drive circuit has a smaller drive capacity than said signal drive circuit.

Semiconductor memory device having self-timing circuit

A semiconductor device with laser-programmable fuses for repairing a memory defect found after production, in which guard rings and fuse patterns are designed to take up less chip space. The semiconductor device has a fuse pattern running parallel to the longitudinal axis of a rectangular guard ring, and patterns branching from the fuse pattern and drawn out of the guard ring in the direction perpendicular to that axis. The semiconductor device also has a plurality of memory cell arrays, each coupled to an I/O port for receiving and sending memory signals. One of those arrays is reserved as a redundant memory cell array for repair purposes. The device further has switch circuits for switching the connection between the I/O ports and memory cell arrays, selecting either default memory cell arrays of the I/O ports or their adjacent memory cell arrays, including the redundant memory cell array.

Precharge circuits comprises PMOS transistors Q and Q each connected between a bit line and a power source potential VDD, PMOS transistors Q Q Q and Q connected between respective bit line pairs, and PMOS transistors Q and Q connected between respective adjacent bit lines of adjacent bit line pairs, wherein the gate electrodes of the PMOS transistors are each connected to a precharge control signal line PCG. The defect caused by omission of transistors from the prior art circuits is compensated by the PMOS transistors Q and Q each of which is required to be provided for two bit line pairs. With this and transistors of adjacent unit precharge circuits are arranged in plain symmetry, there is no need to provide transistors to be directly connected between bit lines *B and B and an average number of PMOS transistors for each bit line pair is less than 2.5.

Precharge circuit with small width

A decoder circuit includes a detecting device which detects a selecting signal for selecting the decoder circuit, a clock-signal supplying device which supplies a clock signal, and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when the detecting device detects the selecting signal.

Decoder circuit and decoding method of the same

A static memory in which memory cells each have the components thereof laid out so that the area of each memory cell can be further reduced in compliance with improvement in technology of separating devices. The static memory includes CMOS memory cells each having two cross-coupled inverters, in each of which an n-channel transistor and p-channel transistor are connected in series with each other. At least one of the contacts used to cross-couple the two inverters is located in a region other than a region enclosed by the diffused sources and drains of the n-channel transistors and p-channel transistors included in the memory cell.

Static memory adopting layout that enables minimization of cell area

A data-hold timing adjustment circuit having resistance wires to which a power-supply voltage is supplied, formed along numerous flip-flops. MOS variable capacitors 3i and 4i (i=1 to n) are connected at one electrode to the data input end of the flip-flops and at another electrode to the resistance wires. The composite capacitance of the MOS capacitors becomes larger as the value of i increases, independent of the voltage level of the data input end of the flip-flops. When the potential of the data input end of the flip-flop shifts from a high/low level to a low/high level, this shift is delayed more as the value of i becomes larger, while the clock input to the flip-flop is delayed more as the value of i becomes larger.

Data-hold timing adjustment circuit

A semiconductor memory device, includes a memory cell array, a row decoder connected to the memory cell array by a plurality of word lines for selecting a word line in response to a first address signal supplied thereto, a column decoder connected to the memory cell array by a plurality of bit lines for selecting a bit line in response to a second address signal supplied thereto, and a data discrimination unit connected to the column decoder by a common data bus for producing an output data signal indicative of the data stored in the addressed memory cell. The column decoder includes a plurality of sense amplifiers each connected to a corresponding bit line for selecting an addressed bit line. The plurality of sense amplifiers are connected to a common data bus for carrying data stored in the addressed memory cell. A plurality of switching devices are provided in correspondence to the plurality of sense amplifiers for selectively transferring the data detected by the sense amplifier to the common data bus. Wherein each of the switching devices includes a bipolar transistor having a collector connected to a power voltage source, an emitter connected to the common data bus, and a base connected to the corresponding sense amplifier for receiving the output signal of the sense amplifier indicative of the data.

Semiconductor memory device with bipolar-FET sense amp

A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.

Logic circuit using bipolar complementary metal oxide semiconductor gate

A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result, the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.

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Kawasaki, Japan

Yasuhiko Maki