Hitachi, Ltd.

Hitachi Computer Engineering Co., Ltd.

Yasuhiko Hatakeyama

Shigeo Nagashima

Hiroshi Murayama

Hitoshi Abe

Toshiaki Arai

Toshiyuki Kinoshita

Shun Kawabe

Yoshio Kiriu

Tomoo Aoyama

Toshimitsu Ando

Shigeko Yazawa

Masakazu Fukagawa

Hiroo Miyadera

Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.

Information processing system

In a disclosed embodiment of the address space control apparatus, each general-purpose register usable as a base register is associated with another general-purpose register in addition to an access register containing a segment table origin. When a general-purpose register is selected as a base register, the contents of its associated general-purpose register are read out and added to the segment table origin from the associated access register to provide an effective segment table origin. In a modification, the access registers are omitted, and the general-purpose register selected as a base register are used to select an entry in a register or register array containing segment table origins in respective entries. In other embodiments disclosed, general-purpose registers are used in different manners to enhance virtual address space control functions.

Address space control apparatus for virtual memory systems

A data processing system capable of implementing at high speeds animating image generation processing and animating image display processing in synchronization with each other, thereby generating and displaying an animating image in a real time. The data processing system uses a given memory area of a storage unit as a screen buffer memory for storing an animating image data for each screen and is provided with an image processor for writing an animating image data for each screen in a screen buffer memory, an image display processor for reading the animating image data for from the screen buffer memory and for generating a display screen graphic signal to be supplied to a display unit and a hardware register circuit having a screen read-out control register corresponding to the animating image data for each screen of the screen buffer memory. The hardware register circuit updates data of the screen read-out control register in synchronization with each of a write operation of an animating image data from the image processor and a read operation of the animating image data to the image display processor. A delivery and a receipt of the data of the animating image data for each screen is carried out at high speeds between the image processor and the image display processor through the screen buffer memory storing the animating image data therefor by a control of the hardware register circuit.

Data processing system

An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

Address conversion for a multiprocessor system having scalar and vector

In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.

Pipeline arithmetic apparatus

A vector processor has a main storage, a main memory control circuit, vector registers, data transfer circuits; an address register group, and vector arithmetic units. The vector processor performs vector arithmetic processings of vector data received from the vector registers and sends the results to the vector registers. For simple vector instructions, the vector processor divides the vector processings and carries out the vector processings in parallel, using a plurality of sets of the above-mentioned data transfer circuits, vector registers and vector arithmetic units. On the other hand, for complicated vector instructions, the vector processor carries out the vector processings without dividing them using the vector registers, data transfer circuits and vector arithmetic units which were designated by the vector instructions.

Vector processor having pair process mode and single process mode

A data processor has a plurality of vector registers capable of reading and writing in parallel; a plurality of ALU's; a plurality of sending circuits, one for each of said vector registers, each for updating a read address for the corresponding vector register requested by a succeeding instruction within such a limit that said read address does not pass a write address for said corresponding vector register requested by a preceding instruction and sending out a read data together with a data valid signal for each updating; circuits for sending the data and the data valid signals from said plurality of sending circuits to the ALU's requested by the corresponding instructions; and circuits, one for each of said ALU's, each for controlling the corresponding ALU such that when the data valid signals have been received from all of the vector registers necessary to execute the instruction which uses the corresponding ALU, the corresponding ALU operates on the data supplied with said data valid signals and sends out a data valid signal.

Growing community of inventors

Hadano, Japan

Yasuhiko Hatakeyama