Nec Corporation

Elpida Memory, Inc.

Nec C Orporation

Yasuhiko Hagihara

Hiroaki Ikeda

Masayuki Mizuno

Kayoko Shibata

Muneo Fukaishi

Hideaki Saito

Shigeto Inui

Atsushi Yoshikawa

Chie Ohkubo

A second DC power-supply voltage that is obtained by outputting a first DC power-supply voltage obtained by converting an AC power supply into a direct current in an AC-DC converter circuit, through a first switch for PWM switching is smoothed and fed to a load as an output DC power-supply voltage. The first DC power-supply voltage is also supplied to a battery through a third switch for PWM switching and the battery is thereby charged. Further, a third power-supply voltage output from the battery is output to the output side of the first switch through a fourth switch for PWM switching.

Uninterruptible power supply apparatus and control method

A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program

A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Stacked semiconductor device

In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections

The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Stacked semiconductor memory device

A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate arrayfor carrying out fine adjustment of the delay time interval of the input signal, capacitancestoandtoconnected to the output side of a specified gate in the first gate array via first switching devicetoa second gate arrayfor carrying out rough adjustment of the delay time interval of the input signal; and a control devicethat adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array

Delay adjustment circuit and a clock generating circuit using the same

A semiconductor integrated circuit includes a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of the second conductivity-type connected in series between the drain of the first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal. The second transistor and at least one and not all of the third transistors have a threshold voltage lower than a threshold voltage of the others of the third transistors.

Semiconductor integrated circuit

A semiconductor integrated circuit enables a drive circuit and a reception circuit to be constituted. The drive circuit drives long wiring in high speed while achieving realization of reduced area when large capacity of load is driven. The reception circuit receives this signal in high speed. There is provided an inverter within the drive circuit. An n-type MOS transistor is adopted as drive transistor. Drive power of the n-type MOS transistor is larger than that of a p-type MOS transistor. It is capable of driving signal with large load in long wiring such as bus line. Thus the drive circuit is realized in that the drive circuit drives the long wiring in high speed while achieving realization of reduced area. Further, it is capable of realizing a reception circuit suppressing through-current during the time period when the signal is changed.

Disclosed herein is a semiconductor integrated circuit comprising: a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of said second conductivity-type connected in series between the drain of said first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal, said second transistor and at least one and not all of said third transistors having a threshold voltage lower than a threshold voltage of the others of said third transistors. The circuit of the present invention including the transistors having the different threshold values can achieve the high speed operation of the circuit, the extension of the signal retention time secured by the reduction of a leakage current and the decrease of the power consumption.

A floating point multiplier includes an exponential part adder for receiving and adding exponential parts of a multiplied value and a multiplying value and outputting an exponential addition result, a binary multiplier for receiving and multiplying mantissa of the multiplied value and the multiplying value and for outputting the multiplication result, an OR gate inputting for receiving a predetermined number of lower order bits of the multiplication result and outputting a logical sum of the lower order bits as a sticky bit, rounding process and normalization process circuit for receiving a predetermined number of higher order bits of the multiplication result and the sticky signal, performing a rounding process and a normalizing process for the higher order bits of the multiplication result on the basis of the sticky bit, coupling a result of normalization with the addition result of the exponential parts and outputting a final multiplication result, and a selection circuit for receiving the final multiplication result and the lower order bits of the multiplication result of the binary multiplier and selectively outputting.

Floating point multiplier capable of easily performing a failure

A multiplier circuit has a partial AND generating portion generating n in number of partial AND's as products of a multiplied value and respective bits of n-bit multiplying value, an intermediate sum generating portion inputting n in number of partial AND's, generating intermediate sums and reducing number of the intermediate sums progressively for finally outputting two intermediate sums, and an adder adding two intermediate sums output from the intermediate sum generating portions for outputting a product of multiplication of the multiplied value and the multiplying value. The intermediate sum generating portion has a plurality of intermediate sum calculating circuits, each of which has a plurality of adders of the type of four inputs and two outputs, connected in parallel, the intermediate sum calculating circuits are connected in a plurality of stages in a tree-like configuration.

Adder and multiplier circuit employing the same

An artificial random-number pattern generating circuit has a plurality of flip-flops each having a set signal input terminal and a clock signal input terminal; a plurality of selectors each of which forwards its output to the corresponding flip-flop and receives a first operation mode signal and/or a second operation mode signal; and an exclusive logical OR gate. The artificial random-number pattern generating circuit functions in three different ways, that is, as an artificial random-number pattern generator, a boundary scanning buffer or an input buffer, in accordance with the combinations of the first and second operation mode signals. The circuit can make not only a diagnosis of failure in the internal circuit of the large-scale integration (LSI) but also overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings for the LSI.

Artificial random-number pattern generating circuit

A multiplying circuit is able to perform a multiplication of n bits.times.n bits at a high speed by increasing the speed of the forming process of the partial products so that the delay time may be inhibited from increasing for a large n, and which can inhibit the chip size from becoming large. A 6-bit multiplier (Y1 to Y6) is divided into bit sets each having plural bits. The thus divided sets are inputted respectively into booth decoders 1A to 1C to generate three-bit interim outputs m1 to m3. On the other hand, partial product generating circuits 2A, 2B and 2C receive a multiplicand X of plural bits to form partial products p1, p2 and p3 respectively by multiplying the multiplicand X with the interim outputs m1, m2 and m3. These partial products p1 to p3 are transformed in a first full adder allay 3 into interim sums r1 and r2. The thus formed interim sums r1 and r2 are added in a second full adder allay 4 with a value. 's' which is prepared by arranging the lowest bits of the interim outputs m1, m2 and m3 by every other bits with '0' therebetween. The thus formed interim sums are defined as r3 and r4. An adder 5 adds up these interim sums r3 and r4 to provide a multiplication output.

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Tokyo, Japan

Yasuhiko Hagihara