Victor Company of Japan, Limited

Yasuhiko Fujii

Susumu Saito

Shinji Nakamura

Takaro Mori

Masami Yamazaki

Yutaka Haramoto

Isao Owaki

Hiroyuki Saito

Mitsuru Kikuchi

A data recording and reproducing apparatus promotes error-free and speedy exchange of data between separate recording media. When desired primary data is to be recorded on a master recording medium, secondary data is added to the primary data in order to detect and correct data errors. The primary and secondary data are recorded on the master recording medium in a plurality of series which differ in recording sequence from each other. The primary data is reproduced from the master recording medium together with the secondary data for the different series at the same time, regardless of their recording sequences. The reproduced primary data is allowed for error check and correction based on the secondary data and is recorded in the slave recording medium.

Digital data duplication apparatus

A method and apparatus for digital magnetic recording of data in which digital data is recorded on a magnetic recording medium after being demodulated by the NRZI (Non-Return-to-Zero Inverted) system and read thereoutof timed to magnetic flux reversal caused by the recorded data on the recording medium. The digital data is encoded in a predetermined manner before the NRZI modulation so that at least part of 'false' bits contained in the digital data is converted into 'true' bits, resulting in an increase in the number of 'true' bits. The encoded data is written into the recording medium after the NRZI modulation. In the event of reproduction of the data from the recording medium, self-clocking occurs to generate a data readout timing. The increased number of 'true' bits insures desirable self-clocking. The data read from the recording medium is decoded to the original digital data.

Digital data transmission system with modified NRZI

A digital signal having a configuration of blocks or frames is recorded via a multi-track record on a first group of tracks, such as odd tracks, of a master tape which is driven at a first direction. Then when recording another digital signal by forming a second group of tracks, such as even tracks, in a second direction which is opposite to the first direction, the digital signal prerecorded on the first group of tracks is derived to produce a speed signal indicative of the tape speed at which the digital signal was recorded on the first group. The speed signal is then compared with a reference signal having a predetermined frequency for producing a control signal, which is used to control the driving speed of the master tape. Thus the second group of tracks is formed with the running speed of the master tape being controlled. As a result, the phase difference between the first and second groups of tracks is constant throughout the entire length of the master tape. The speed signal may be derived from a synchronous signal recorded on a control track, which may be formed when forming the first group of tracks.

Tape speed control for producing a master tape carrying a digital signal

A digital signal comprising a plurality of data blocks each comprising a plurality of data words and a parity word is transmitted without a synchronous word or signal indicative of the boundary between two consecutive data blocks. The parity word comprises a plurality of bits each generated from bits of a corresponding row in the original data words in the data block. When receiving the digital signal, the digital signal is first stored in a memory and a plurality of sets of bits in each row is read out to provide parity checking. As a result of parity checking, absence of parity error will be detected in connection with a particular set of bits, and this particular set of bits in each row can be treated as a single row constituting the original data block. The stored digital signal will be read out and output on the basis of information of absence of parity error so that synchronism of data blocks can be established to accurately restore original analog information from the received digital signal having no synchronous word.

Method and circuit arrangement for synchronous detection

Each block of data having information data and redundant bits is transmitted without any synchronous signal bit word, while transmitted data is processed to find the boundary between consecutive data blocks so that a synchronous signal will be produced at the receiving end. The system for producing the synchronous signal comprises a cyclic redundancy check (CRC) circuit, a frequency divider for dividing the frequency of shift clock pulses and a reset pulse generating circuit. The reset pulse generating circuit is responsive to the output signal from the frequency divider and the shift clock pulses to produce periodically first and second reset pulses with which the CRC circuit and the frequency divider are initialized. The reset pulse generating circuit is further responsive to an error signal from the CRC circuit so that further first and second reset pulses are produced with which the CRC circuit and the frequency divider are initialized again. Initialization is repeated until the frequency divider is synchronous with the bits of the data blocks, and once synchronizm is established, the output signal from the frequency divider can be regarded as the synchronous signal indicative of the boundary between any two consecutive data blocks.

Method and system for producing a synchronous signal from

A system for obtaining synchronized reproduction from a plurality of reproducing apparatuses by obtaining mutually synchronized reproduced signals from a plurality of reproducing apparatuses, where the plurality of reproducing apparatuses respectively reproduces recorded signals from a recording medium in which mutually identical address signals are recorded for each predetermined data signal block. The system for obtaining synchronized reproduction comprises a control circuit for controlling reproducing operations of the plurality of reproducing apparatuses so that one reproducing apparatus with respect to the other reproducing apparatus of the plurality of reproducing apparatuses performs reproduction in a state advanced by a predetermined quantity on the recording medium, a detection circuit for comparing and detecting a difference between address signals reproduced by the plurality of reproducing apparatuses, and a memory device controlled for writing-in and reading-out operations by a detection output from the detection means, for producing a reproduced signal from the one advanced reproducing apparatus after delaying the reproduced signal so as to be in synchronism with a reproduced signal from the other reproducing apparatus.

System for obtaining synchronized reproduction from a plurality of

A data acquisition circuit is adapted to receive information data, a synchronization pulse and a clock pulse which is transmitted at twice as high as the transmission rate of the information data. The clock and synchronization pulses are processed into a conditioning pulse for a divide-by-two frequency divider so that it conditions the divider to respond to the clock pulse by generating a data acquisition pulse at a frequency corresponding to the transmission rate of the information data in a correct phase relationship therewith.

Data acquisition circuit

A signal processing circuit has a circuit organization having a pair of crosstalk circuits respectively including at least delay circuits each of a delay time .tau. and adapted to add or cancel crosstalk components to or in input signals in correspondence with the transfer characteristics between sound sources and the two ears of a listener. Each crosstalk circuit has means for attenuating components of frequencies represented by (2n-1/2.tau.) (where n is a positive integer).

Signal processing circuit

A phase-shifting circuit comprises a first transistor circuit having a base to which an input signal is applied, first and second resistors of equal resistance values connected mutually in series and between an emitter of the first transistor circuit and ground, a third resistor connected at one terminal thereof to the emitter of the first transistor circuit, a capacitor connected between the other terminal of the third resistor and ground, and a second transistor circuit having a base connected to said other terminal of the third resistor and an emitter connected to the junction between the first and second resistors, an output signal being led out from a collector of the second transistor circuit.

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Yamato, Japan

Yasuhiko Fujii