Fijitsu Limited

Yasuhide Shibata

Takaharu Ishizuka

Takumi Takeno

Takato Noda

Fumitake Sugano

Katsunori Takeshita

Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units

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Kawasaki, Japan

Yasuhide Shibata