Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Yasuharu Takenaka

Takashi Takemoto

Isao Mihara

Masaaki Oka

Junichi Fujita

Masaharu Yoshimori

Sumihiko Yamamoto

Tomohiro Koizumi

Takasi Takemoto

An image processing apparatus includes a first and second Z value calculators that calculate a polygon Z value and a block Z value, respectively. The polygon Z value is a coordinate value of a pixel located at a closest point to a viewpoint. The block Z value is a coordinate value of a pixel located at a closest point to the viewpoint in a block. The apparatus also includes a Z value selector that selects a Z value of a pixel closer to the viewpoint from the polygon Z value and the block Z value as an estimate Z value; and a hidden-surface removal unit that eliminates drawing of the polygon in the block when a pixel corresponding to the estimate Z value is located at a farther point from the viewpoint than a pixel located at a farthest point from the viewpoint.

Apparatus and method for performing hidden surface removal and computer program product

Computer graphics data coding apparatus includes unit configured to acquire computer graphics data items, unit configured to pre-process acquired computer graphics data items, controlling/coding unit configured to subject pre-processed computer graphics data items to process for controlling number of codes to be finally output, to generate codes, accumulation unit configured to accumulate parts to be subjected to entropy coding, which are contained in generated codes, calculation unit configured to calculate entropy information based on accumulated parts, and generate code words based on entropy information, entropy information indicating amount of entropy, entropy coding unit configured to subject generated codes to entropy coding based on generated code words, to generate entropy codes, extraction unit configured to extract, from entropy information, minimum information for decoding, extracted-information coding unit configured to code minimum information in order to reduce amount of minimum information, and output unit configured to output entropy codes and coded minimum information.

Computer graphics data coding apparatus, decoding apparatus, coding method and decoding method

A fractional arithmetic unit for performing fractional arithmetic operations of different numerators and a common denominator with different precisions as required, the fractional arithmetic unit, including a reciprocal number arithmetic logic unit; and a multiply arithmetic circuit configured to multiply a numerator and a reciprocal number of the denominator as obtained by the reciprocal number arithmetic logic unit. A precision of a calculation performed by the reciprocal number arithmetic logic unit is changed in accordance with a precision as required for each of the fractional arithmetic operations. The multiply arithmetic circuit outputs a result of multiplication as a result of the fractional arithmetic operation, and the results of the fractional arithmetic operations are output with different precisions.

Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium

Image composing method and apparatus

An image processing apparatus suitable for three-dimensional high speed image processing can be realized by improving the memory address control and the access method, that is, by improving the data transfer speed between the image memory and the other unit. The image processing apparatus comprises the pixel forming unit (1) for forming frame data for each pixel; an image memory (2) constructed by a plurality of banks (3, 4) to which row addresses are inputted through a row address input system (6) and column addresses are inputted through a column address input system (7); and the DRAM controller (5) for controlling the image memory (2). The DRAM controller (5) controls the image memory (2) in such a way that the screen is divided into a plurality of rectangular regions so that the frame data of one rectangular region can be stored in one page of the image memory (2); the frame data in the adjoining rectangular regions are allowed to correspond to the two different banks (3, 4) of the macro cell; and the column addresses can be generated continuously when any of the banks is being accessed, so that any addresses can be accessed continuously in the same page. Further, the DRAM controller (5) controls the address sequence predicting circuit (8) in such a way that the banks to be accessed in the future can be accessed immediately after the bank to be accessed is switched.

Image processing apparatus having improved memory access for high speed

A graphic drawing processing system has a frame memory including a drawing data area for holding data for drawing on a display, and an offscreen area for holding source data for a specified pattern which is not displayed on the display. The system further includes a coordinate convertor for obtaining pattern data corresponding to picture elements to be drawn, based on pattern source data in the offscreen area, and a memory for storing one portion of the pattern source data in the offscreen area.

Growing community of inventors

Kanagawa, Japan

Yasuharu Takenaka