Fujitsu Corporation

Yasufumi Honda

Kenji Suzuki

Takashi Koguchi

Takuya Kitamura

Hiroshi Ikeda

Kazuya Takaku

Masaharu Yoshiyama

To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.

Memory control device

An estimating unit estimates, when there is a request for data in a system in which an error checking unit of data is formed with a plurality of memories each of which is a dual memory having an independent address line, whether an error has occurred on the address line based on a result of an error checking for data related to the request. A control unit generates, when it is estimated that an error has occurred on the address line, error data of the data related to the request, and controls the memory in such a manner that one line of the dual memory is disabled by switching the data related to the request to generated error data.

Memory controller and method of controlling memory

A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Soft error correction method, memory control apparatus and memory system

The present invention provides a control method for an error detection & correction apparatus, comprising a plurality of data processing apparatuses which reside in a data communications path and partake in exchanging data by the unit of error correcting code, and a plurality of information exchange paths which are installed between the plurality of data processing apparatuses; and generating a true syndrome by exchanging a partial syndrome relating to a part of the data partaken by each of the data processing apparatuses by way of the information exchange paths, comprising the step of exchanging renewal information relating to a part of the data partaken by each of the data processing apparatuses with the other data processing apparatus by way of the information exchange path.

Control method for error detection & correction apparatus, error detection & correction apparatus, and computer-readable storage medium storing control program for error detection & correction apparatus

A technology for distributing a content to wireless portable terminals through P2P by using a short-haul radio scheme. A wireless terminal detects another wireless terminal capable of communicating with the first wireless terminal, receives a content, receives control information on the content, and carries out control according to the control information. The present invention wherein communication reflects the intention of the content providing side since wireless terminals perform communication according to the control information, a content distributing method, a wireless terminal, a content distribution program, and a content distribution system are disclosed.

Content distributing method

A clock apparatus has a first clock unit, a backup power supply unit, a second clock unit, and a control unit. The first clock unit is used to count time, and the backup power supply unit is used to supply a backup power voltage to the first clock unit, when a general power supply unit does not supply a general power voltage to the clock apparatus. The second clock unit has a higher accuracy than the first clock unit. The control unit is used to adjust the time counted by the first clock unit in accordance with a specific period counted at the second clock unit, and the control unit is also used to control the resetting of an operation of the second clock unit, when the general power supply unit starts to supply the general power voltage to the clock apparatus after the general power supply unit has been stopped. Consequently, the clock apparatus has a high accuracy corresponding to the second clock unit, and has a low consumption power when the general power supply unit cannot to supply the general power voltage to the clock apparatus, so that an improved batter backup operation for the clock apparatus can be realized.

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Kawasaki, Japan

Yasufumi Honda