Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Yasue Yamamoto

Masanori Shirahama

Yasuhiro Agata

Toshiaki Kawasaki

Hirohito Kikukawa

Shinichi Sumi

Ryuji Nishihara

A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line.

Semiconductor memory device

In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

Nonvolatile semiconductor memory device

A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

System LSI

A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.

Electrical fuse circuit

A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A gate of the MOS transistor is connected electrically to one of the drain and the source thereof in each stage, and a substrate for at least one pair of adjacent MOS transistors are connected electrically to one of the drain and the source of one of the pair. The back bias effect is suppressed, and the layout area is reduced. Further, a plurality of booster capacitors connected in series are provided in succeeding stages, thereby suppressing degradation of breakdown voltage of each capacitor.

Charge-pump circuit

A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.

In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.

Semiconductor memory device and semiconductor integrated circuit system

Electrical fuse blocks () of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (). The electrical fuse block () includes a program shift register block () made up of shift registers () which are disposed for the respective electrical fuse cores (), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors () of the electrical fuse cores (). When performing programming according to programming decision signal PBn, the program shift register block () transmits the program enable signal FPGI. When not performing programming, the program shift register block () skips the program enable signal FPGI.

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Osaka, Japan

Yasue Yamamoto