Nippondenso Co., Ltd.

Denso Corporation

Yasuaki Tsuzuki

Akira Kuroyanagi

Toshio Sakakibara

Satoshi Shiraki

Yutaka Tomatsu

Makoto Ohkawa

Takayuki Sugisaka

Toshiaki Nishizawa

Ichiro Ito

Akito Fukui

Atsumi Takahashi

Tomio Yamamoto

Masami Yamaoka

Yoshifumi Okabe

An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Method of etching metallic thin film on thin film resistor

The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.

Vertical type semiconductor device and gate structure

An intelligent power element has integrated DMOS transistors and control elements such as NMOS transistors. Impurity concentration inside a channel well (4) of each DMOS transistor is denser than that at the surface thereof. This results in reducing the reach-through withstand voltage of the DMOS transistor to less than that of the NMOS transistor. As a result, a reach-through phenomenon occurs on the DMOS transistor having a higher allowable (withstand) current before it occurs on the NMOS transistor having a lower allowable current. To provide the same effect, the reach-through withstand voltage of the DMOS transistor may be decreased by forming an internal high concentration well (201) at an upper part of a deep main well (31) of the DMOS transistor. The well (201) is shallower than the main well (31) and does not extend under a gate electrode (71).

Method for producing semiconductor device having DMOS and NMOS elements

A power DMOS semiconductor device is producible with standard processes and provides improved current detecting accuracy. The device involves main wells (41), subwells (42), and a line well (43), which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate (1) with well forming impurities. The line well surrounds the subwells with a predetermined distance away from the subwells, to relax an electric field on the surface of the substrate. Gate electrodes (71, 72) are patterned to form a line opening (10), which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

Method of producing a semiconductor device having accurate current

A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.

Vertical type semiconductor with main current section and emulation

Growing community of inventors

Anjo, Japan

Yasuaki Tsuzuki