Sharp Kabushiki Kaisha Corporation

Yasuaki Hirano

Shuichiro Kouchi

Toshio Hata

Yoshiji Ohta

Hiroaki Onuma

Yasumichi Mori

Tsuyoshi Ono

Makoto Hirota

Kenichi Murakoshi

Yoshihisa Sekiguchi

Hidekazu Fujii

A light emitting device includes a semiconductor light source device including a plurality of semiconductor light emitting elements, a wavelength conversion member that converts a wavelength of irradiation light from the semiconductor light source device, a concentrating lens that concentrates the irradiation light from the semiconductor light source device, and a cylindrical holder. The semiconductor light source device, the wavelength conversion member and the concentrating lens is supported by a support portion provided in an inner diameter portion of the cylindrical holder.

Light emitting device

Provided is a backlight unit capable of reducing luminance unevenness. The backlight unit includes a plurality of dot light sources and a light guide plate in which a predetermined side surface serves as a light incident surface for introducing light from the plurality of dot light sources. The plurality of dot light sources are classified into a first light source group and a second light source group. A mount point of the first light source group and a mount point of the second light source group are displaced from each other in a thickness direction of the light guide plate. A total luminance of the first light source group is higher than a total luminance of the second light source group.

Backlight unit and display device including the same

A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

Non-volatile semiconductor memory device and erasing control method thereof

In the nonvolatile semiconductor memory device of this invention, a program control circuitsets the threshold value of a first reference cell RFCby means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFCwith the threshold value of a second reference cell SRC executed by a sense amplifierfor trimming. The compare of threshold values by the sense amplifierfor trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFCTherefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

Nonvolatile semiconductor memory device

A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

Non-volatile semiconductor memory device and data write control method for the same

This nonvolatile semiconductor memory device includes a word line regulator circuit , which supplies a voltage to a word line, a program/erase control circuit , which outputs a write control signal to the word line regulator circuit , and a pulse voltage step width storage circuit , which stores information of a voltage increment &Dgr;Vg. The word line regulator circuit supplies a voltage to a word line according to the write control signal from the program/erase control circuit based on the information of a voltage increment &Dgr;Vg stored in the pulse voltage step width storage circuit . A voltage increment &Dgr;Vg by which a threshold voltage change of a memory cell becomes a predetermined voltage can be set for each chip by the pulse voltage step width storage circuit . Consequently, a highly reliable multi-valued write operation can be performed.

In a memory cell array, a floating-gate field-effect transistor connected to a word line and a bit line is disposed in a matrix configuration. The floating-gate field-effect transistor is composed of a source and a drain formed inside a P-type well provided inside an N-type well on a P-type semiconductor substrate, a floating gate formed over between the source and the drain with a tunnel oxide interposed therebetween, and a control gate formed on the floating gate with an interlayer insulating film interposed therebetween. When an erasing pulse is applied, a voltage of 6V is applied to the P-type well with use of a first high-voltage pumping circuit, while a voltage of 9V is applied to the N-type well with use of a second high-voltage pumping circuit. This makes it possible to provide a highly reliable nonvolatile semiconductor memory device capable of preventing occurrence of latchup.

Nonvolatile semiconductor memory device capable of preventing occurrence of latch-up

In a nonvolatile semiconductor memory device, a voltage Vpp of 12 V applied to an external terminal is dropped by a resistance element of 3500 &OHgr; to a voltage Vrpin. Vrpin is inputted to a regulator circuit to output a stabilized voltage Vpll of 5 V, so that Vpll is applied to a common source line as an erase pulse voltage. Termination of a first erase pulse application is judged by a level detection circuit based on a result of comparison between a reference voltage Vref of 11 V and an input voltage Vrpin which begins with 5 V upon start of the erase operation. Thus, since a large voltage magnitude of the input voltage is secured, a variation in the threshold voltage of a memory cell after the termination of the first erase pulse application can be made small, thereby preventing degradation of the erase speed.

Nonvolatile semiconductor memory device and method of erasing the same

In a nonvolatile semiconductor memory device, overerase-verify in an erase operation is conducted in units of bit lines in a batch. A cell current of a reference cell and voltage applied to a word line of a main cell are set so as to have a detection level at which there can be one or no memory cell having a threshold voltage of 0.5 V at time of one overerase-verify operation and a leak current of an unselected memory cell can be 1 &mgr; A or lower in a normal operation. Thus, the number of verify times in the overerase-verify is reduced to shorten period of time in the overerase-verify and thereby achieve high-speed erase. Furthermore, a cell current can be reduced to achieve lower power consumption.

Nonvolatile semiconductor memory device and method of detecting overerased cell

For erasing a block , a voltage Vpp is applied to select word lines WL -WL , while a voltage Vneg is applied to each of the substrate (well) and sub-bit lines SBL -SBL . Also, a voltage Vneg is applied to word lines WL -WL of a non-select block , while the voltage Vneg is applied to the substrate (well) and the sub-bit lines SBL. Thus, the voltage Vneg is applied to the control gates, sources and drains of all the memory cells within the non-select block and the substrate (well), so as to make them equal in voltage to one another. Therefore, there occur no mis-reads during the reading. Further, the capacity between the non-select word lines WL and the substrate (well) can be neglected, and the occupancy ratio of the charge pump for use of supply of the negative voltage can be reduced by an extent corresponding to 90% or more of the conventional counterpart. As a result, mis-reads due to substrate disturb during the erasing can be prevented.

Erase method for nonvolatile semiconductor storage device and row decoder circuit for fulfilling the method

This method has a step of performing a write-before-erase operation (S S ) and a step of performing an erase operation (S S ) for a memory cell. A voltage application condition upon the write-before-erase operation is relaxed in comparison with a voltage application condition upon a usual write operation so that a threshold voltage distribution of memory cells after the write-before-erase operation is substantially different from a threshold voltage distribution of memory cells after the usual write operation. According to this data erase method for a nonvolatile semiconductor memory device, stress applied to each memory cell by the write-before-erase operation can be reduced, and hence reliability of a memory cell can be improved.

Nonvolatile semiconductor memory device and data erase method therefor

A p-MOS transistor is connected to an intermediate node . A level shifter supplies an output signal hresetb to a gate of the p-MOS transistor based on a signal Reset. Then, in an initial state until a pump operation is started, the signal Reset is set at &ldquo;H&rdquo; to turn on the p-MOS transistor . Thus, a positive charge of the intermediate node is discharged via the p-MOS transistor and a negative charge is discharged via an N-well of the p-MOS transistor so that the potential of the intermediate node becomes about 0.7 V. Therefore, even when the pump operation is started and the p-MOS transistor is turned off, the maximum voltage applied to each of the capacitors C , C is 4 V, and exceeding of the withstand voltage of a capacitor insulating film can be prevented.

Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device

A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.

Nonvolatile semiconductor memory well voltage setting circuit without latchup and semiconductor memory device provided with the circuit

None of memory cells employed in a memory cell array is not put into an overerased state even if erase pulse application for 300 ms is executed four times in a fast cell out of the memory cells. Accordingly, one block in the memory cell array is divided into four regions, and the pre-erase written state of each region is written into an erase frequency storage memory that has memory cells of 3-bit for storing an erase frequency. Then, by referring to the contents of the erase frequency storage memory , pre-erase write and write verify are executed in one region only once every four erase operations. Thus, the region of the pre-erase write executed during one erase operation is made to be one-fourth of the conventional region, shortening a pre-erase write pulse applying time and a write verify time and reducing an increase in the pre-erase write time ascribed to a reduction in operating voltage.

Nonvolatile semiconductor memory device capable of reducing pre-erase write time and erase method therefor

In an erase method for a nonvolatile semiconductor memory device in which a memory cell array is divided into blocks, an erase pulse application for erasing information, a first verify operation for verifying a threshold voltage shift due to the erase pulse application and a second verify operation for verifying whether excessive erasure has occurred due to the erase pulse application are performed for memory cells connected to one word line in a certain block. When a memory cell excessively erased is found by the second verify operation, a soft program operation for the memory cell is performed after the second verify operation. The erase pulse application, the first verify operation, and the second verify operation are executed word line by word line in the block.

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Tenri, Japan

Yasuaki Hirano