Qualcomm Incorporated

Yasser Ahmed

Sachin Ajit Devamare

Ying Duan

Shih-Wei Chou

Abhay S Dixit

Harry Huy Dang

Jing Wu

Vinaya Ajjampura Rajappa

An interface circuit has a data recovery circuit, a protocol interface circuit and a controller or processor that can be implemented using a finite state machine. The data recovery circuit may be configured to receive a stream of symbols over three wires of a serial bus according to a high-speed mode defined by a Mobile Industry Processor Interface Alliance C-PHY protocol. The protocol interface circuit may be coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine may be configured to cause the data recovery circuit to be disabled when an end of transmission is indicated in a first end-of-transmission signal received from the protocol interface circuit.

Automatic high-speed shutdown for C-PHY receiver

A communication interface circuit has a shift register configured to convert a serial stream of 3-bit symbols to a parallel multi-symbol word comprising a plurality of symbols ordered in accordance with time of arrival at an input of the shift register; a set of symbol comparators, each symbol comparator being configured to determine whether a pattern of symbols in the parallel multi-symbol word indicates presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is active when a synchronization pattern is detected in the serial stream of 3-bit symbols, and further configured to suppress the control signal when at least one of the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.

C-PHY receiver corrupt post pattern filter

A video processing circuit has a bus interface circuit configured to communicatively couple the video processing circuit to an imaging device over a multidrop differential serial link; detector circuits configured to detect sequentially occurring signaling states of the multidrop differential serial link, the sequentially occurring signaling states preceding a transition of the bus interface circuit from a low-power mode to a high-speed mode; and a controller configured to: cause the bus interface circuit to receive data transmitted over the multidrop differential serial link in the high-speed mode when a duration of each signaling state in the sequentially occurring signaling states exceeds a minimum duration defined for the each signaling state; and cause the bus interface circuit to return to the low-power mode when one signaling state of the sequentially occurring signaling states does not exceed a corresponding minimum duration defined for the one signaling state.

Programmable hot plug-in controller for a multidrop differential serial bus

A processing circuit coupled to an imaging device includes a bus interface circuit configured to communicatively couple the processing circuit to the imaging device over a multidrop differential serial link, detector circuits configured to detect a plurality of sequentially occurring signaling states of the multidrop differential serial link, the plurality of sequentially occurring signaling states related to transmissions of data packets over the multidrop differential serial link, and a controller. The controller is configured to discard data packets received after the imaging device is powered on or initialized and until the imaging device is indicated to be in an active operating state, count sequences of transitions between a first signaling state of the multidrop differential serial link and a second signaling state of the multidrop differential serial link, and indicate that the imaging device is in the active operating state after a preconfigured number of data packets have been discarded.

Programmable initial packets rejection in a display system interface

A communication interface circuit has a deserializer configured to convert a serial stream of 3-bit symbols received from a three-wire serial bus to a parallel multi-symbol word comprising a plurality of symbols ordered in accordance with time of arrival at an input of the deserializer, detection circuits configured to determine whether a pattern of symbols in the parallel multi-symbol word indicates a corrupt data packet, and a finite state machine configured to activate one or more flags responsive to feedback received from the detection circuits. each flag can be configured to cause termination of reception of the corrupt data packet when the each flag is active.

Corrupt packet detector for C-PHY receiver

System, methods and apparatus are described that support multimode operation of a data communication interface. An apparatus includes a physical layer interface coupled to a serial bus and configurable for a high-speed mode of communication and a low-speed mode of communication, and a rate detector configured to receive a clock signal from the serial bus, and to use a reference clock to determine a unit interval representative of a data rate of the serial bus. The apparatus may also include interval calculation logic configured to determine an interval related to timing of a data signal transmitted on the serial bus, the interval having a duration expressed as a number of cycles of the reference clock. The physical layer interface may be configured to use the interval to capture data in the data signal.

MIPI D-PHY receiver auto rate detection and high-speed settle time control

Methods, apparatus, and systems for monitoring and measuring signal characteristics for signals received over a multi-wire, multi-phase interface are disclosed. Signals present on each line of a 3-line communication interface are sampled using auxiliary samplers having a programmable time delay to delay the sampled signal by a set time, as well as a programmable voltage offset. The auxiliary sampler outputs are compared with direct line samples of signals on each of the three lines to generate error signals. From this comparison, an array of error signal data occurring over a particular sampling period may be generated. In turn, waveform characteristics can be determined from the error signal data, such as an eye-pattern. Furthermore, skew measurement may further be effectuated using the auxiliary samplers but determining the time difference of when the error signals of the different wires cross a predetermined threshold.

Signal monitoring and measurement for a multi-wire, multi-phase interface

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

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San Diego, CA, United States of America

Yasser Ahmed