Tokyo Shibaura Electric Co., Ltd.

Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Tokai University Educational System

Yasoji Suzuki

Kiyofumi Ochii

Tetsuya Iida

Hideharu Egawa

Tomohisa Shigematsu

Kenji Matsuo

Yukihiro Saeki

Tadashi Maruyama

Hiroyoshi Murata

Kenshi Manabe

Eiji Masuda

Itsuo Sasaki

Yukio Wada

Koji Matsuki

Chikara Sato

Isao Abe

Hirofumi Kato

Masanori Nakai

Yukuya Tokumaru

Fuminari Tanaka

Mitsuhiko Ueno

Kazuo Satou

Teruaki Tanaka

Makoto Yoshizawa

Toshio Yanagisawa

Kazuyoshi Yamamoto

Hirozi Asahi

Isao Arita

Minoru Takada

Hiroyuki Hamagawa

Hiroaki Suzuki

Akira Yamaguchi

Akira Takiba

Tatsuo Sakaue

Kazuyoshi Shinada

Osamu Matsumoto

Yoshiaki Arimura

Masataka Hirasawa

Yoshinori Higuchi

Ichiro Kobayashi

Shouji Abou

Nobuyuki Kamimaru

Ryuzo Shiraki

Yasushi Sato

Yasuo Shono

Tadashi Kuroda

Yoshihisa Shiotari

Yoshio Kaneko

Nawoyuki Kokado

Yukinori Kudo

Ochii Kiyofumi

Susumu Kouyama

Takeshi Hitotsuyanagi

Hiroshi Osanai

Yasushi Satoh

Toru Tanaki

Naoto Ide

A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit or the second gray-level pattern generating circuit when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Multi-gray level display apparatus and method of displaying an image at many gray levels

A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.

Voltage transfer circuit and a booster circuit, and an IC card

A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Multi-gray level display apparatus and method of displaying an image at

On a light exit surface which is the first principal plane of a light guide, multiple projections are fabricated in specific rows. These projections have light exit surfaces and continuous multiple slopes, and are fabricated from optically identical materials having the same refractive index as the substrate of the light guide. The slope farthest from the light entry edge surface is formed as a light exit surface, i.e., a surface which breaks the conditions for the total reflection of the incident light. On the other hand, the slope nearest the light entry edge surface which is the total reflection surface is formed such that the incident light is totally reflected.

Light guide and liquid crystal display device using it

This invention provides a TAB type semiconductor device in which a plurality of lead pattern regions are formed on a film-like tape formed of an insulating resin, and LSI chips are inner lead-bonded onto the corresponding lead pattern regions. A linear reference potential supply wiring pattern is formed on one edge portion in the widthwise direction of a formation surface of the lead pattern regions on the tape to extend in the tape extending direction. The wiring pattern is electrically connected to a reference potential supply lead (14A) of each lead pattern region.

TAB type semiconductor device and method of manufacturing the same

In a nonvolatile semiconductor memory system comprising a memory chip and a batttery for driving the memory chip, the memory chip includes a memory-cell matrix, a row decoder, a first level-shifting circuit for shifting the level of the output of the row decoder, a column-selecting circuit, a column decoder, a second level-shifting circuit for shifting the level of the output of the column decoder, a sense amplifier, a third level-shifting circuit for shifting the level of the data which is to be written into the memory-cell matrix, a voltage-booster circuit, a timer circuit, and an oscillator circuit. The nonvolatile semiconductor memory system operates stably when driven by a low voltage or by a voltage over a broad range.

Nonvolatile semiconductor memory device incorporating level shifting

A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate for deriving a logic output of two signals. The 2-input logic gate is constituted by connecting two 3-state circuits in a wired OR configuration. One of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal of the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Likewise, the other 3-state circuit includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Each of the data input terminals of the 3-state circuits is supplied with a desired one of the first signal, an inverted signal of the first signal, a '0' level signal, and a '1' level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.

Programmable logic circuit using wired-or tristate gates

A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.

Semiconductor circuit

A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

Power supply switching circuit

A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Complementary semiconductor device

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Nonvolatile semiconductor memory device with a double gate structure

In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

Nonvolatile semiconductor memory

High density semiconductor circuit using CMOS transistors

A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

Nonvolatile floating gate semiconductor memory device

Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.

Complementary MOSFET logic circuit

Growing community of inventors

Ayase, Japan

Yasoji Suzuki