International Business Machines Corporation

Yasir Sulehria

Oleg Gluschenkov

Alexander Reznicek

Bahman Hekmatshoartabari

Ekmini Anuja De Silva

Devika Sil

Ruilong Xie

Devendra K Sadana

Veeraraghavan S Basker

Steven J Holmes

Julien Frougier

Nelson M Felix

Indira P Seshadri

Martin O Sandberg

Adra Carr

Luciana Meli Thompson

Shanti Pancharatnam

Marinus Johannes Petrus Hopstaken

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

Enhanced linerless vias

A Josephson Junction qubit device is provided. The device includes a substrate of silicon material. The device includes first and second electrodes of superconducting metal. The device may include a nanowire created by direct ion implantation on to the silicon material to connect the first and second electrodes. The device may include first and second superconducting regions created by direct ion implantation on to the silicon material, the first superconducting region connecting the first electrode and the second superconducting region connecting the second electrode, with a silicon channel formed by a gap between the first and second superconducting regions.

Josephson junction device fabricated by direct write ion implantation

A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.

Stackable symmetrical operation memory bit cell structure with bidirectional selectors

Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

Large grain copper interconnect lines for MRAM

A harden gap fill dielectric material that has improved chemical and physical properties is formed laterally adjacent to a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode structure of a memory structure. The harden gap fill dielectric material can be formed by introducing, via ion implantation, a bond breaking additive into an as deposited gap fill dielectric material layer and thereafter curing the gap fill dielectric material layer containing the bond breaking additive. The curing includes UV curing alone, or UV curing in combination with laser annealing. The curing employed in the present application does not negatively impact the MTJ pillar or top electrode structure.

MRAM devices containing a harden gap fill dielectric material

Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100&#xb0; C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.

Post-lithography defect inspection using an e-beam inspection tool

A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.

Growing community of inventors

Latham, NY, United States of America

Yasir Sulehria