Intel Corporation

Yasir Mohsin Husain

Nicolas L Irizarry

Balaji Srinivasan

Jaydip Bharatkumar Patel

Ashraf B Islam

Everardo Flores, Iii

Neeladri Sain

Xuming Zhao

Noble Narku-Tetteh

Ripudaman Singh

An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.

Apparatus, method and system to implement a dual VDM scheme on a three-dimensional memory architecture

A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.

NOR gate based local access line deselect signal generation

Techniques for controlling current through memory cells is disclosed. In the illustrative embodiment, a fine-grained current source and a coarse-grained current source can both be activated to perform an operation on a phase-change memory cell. The coarse-grained current source is briefly activated to charge up the capacitance of an electrical path through the memory cell and then turned off. The fine-grained current source applies a current pulse to perform the operation on the memory cell, such as a reset operation. By charging up the electrical path quickly with the coarse-grained current source, the fine-grained current source can quickly perform the operation on the memory cell, reducing the thermal disturbance caused by the operation on nearby memory cells.

Technologies for controlling current through memory cells

A method, apparatus and system. The method includes: generating a feedback voltage Vin a feedback circuit coupled to one of a bitline node (BL) or a wordline node (WL) of each of a plurality of memory cells of a memory array, the feedback voltage to, in a thresholded state of said each of the memory cells, counteract a decrease in an absolute value of a voltage Vat said one of the BL or WL; generating, in a reference circuit, one of a reference voltage Vto track a feedback voltage of the feedback circuit or a mirror current Ito track a current Ithrough said each of the memory cells; and providing one of values for both Vand V, or for an output voltage Vcorresponding to I, to a sense circuitry, the sense circuitry to determine a logic state of said each of the memory cells based on a comparison of Vwith Vor based on V.

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Folsom, CA, United States of America

Yasir Mohsin Husain