Cadence Design Systems, Inc.

Yashu Gupta

Sachin Shrivastava

Ankur Chaplot

Pardeep Juneja

Nikhil Garg

Jean-Marc Bourguet

Joyjeet Bose

Michaela Guiney

Sankalp Srivastava

An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.

Method, system, and product for generating and maintaining a physical design for an electronic circuit having sync group constraints for design rule checking

The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.

System and method for visualization in an electronic circuit design

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Greater Noida, India

Yashu Gupta