Cadence Design Systems, Inc.

Yaron Peri-Glass

Sandeep Pagey

Shabd Swarup V

Alok Jain

Yonatan Ashkenazi

Nadav Chazan

Tal Tabakman

Axel Siegfried Scherer

Frank Armbruster

Ronen Shoham

Dan Leibovich

Don J O'Riordan

Erica Wickstrom Brand

Anuja Jain

F Erich Marschner

A system and method is described in which the state of the art in automated software applications is significantly improved. According to some approaches, interface testing is implemented and based upon a verification language and a verification environment. The system and method support the concepts of constrained random test generation, coverage, constrained random generation, and dynamic checks.

Method and system for testing and analyzing user interfaces

A system and method are provided for enhanced navigation along execution time and code space in a debugger to assist a user in remediating errors, streamlining, or reverse engineering a computer program and the source code thereof. Snapshots of system states are recorded, a causality tree of commands is constructed through execution of the program to be debugged, and an intelligent display of system states captured during runtime and indexed or cross-referenced by time are displayed to the user in an intelligent manner to aid the user with certain debugging tasks. Additionally, further features in assisting the user to locate a root cause of an error or unexpected value and remediate that cause are also provided.

System and method for debugging computer program based on execution history

Disclosed are methods, systems, and articles of manufacture for synchronizing a software verification flow of an application under test (AUT) that uses a user interface. Various embodiments of the methods identify generic application programming interface(s) (API(s)), map menu items of the AUT to logical names, and generate generated API(s) based on the generic API(s) and the mapping results. Some embodiments further generate a custom API by using generated API(s) and implement synchronization accordingly. Some embodiments are directed at a hardware system for performing various methods, while some other embodiments are directed at an article of manufacture for storing a sequence of instructions for various methods disclosed herein.

Methods, systems, and articles of manufacture for synchronizing software verification flows

Disclosed are methods, systems, and articles of manufacture for synchronizing a software verification flow of an application that uses a user interface. Various embodiments comprise implementing a menu item as a widget and identifying an operation associated with the menu item. A synchronizer is further identified or created for the operation and then registered with the operation such that the synchronizer is activated when the operation is invoked during the software verification flow. Once activated, the synchronizer takes over control of the verification flow and prevents the verification flow from proceeding until a criterion is fulfilled. The synchronizer may be reused among different tests, and the same test case may be rerun on different machines with different computing performance and workloads without producing false positives or false negatives.

Methods, systems, and articles of manufacture for synchronizing software  verification flows

An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach provides relative comparison of coverage of the nodes and allows the user to identify whether there is any missing coverage, and if so, whether the missing coverage evenly balanced. This information is very useful for the decision made by the user regarding overall coverage and steps to be taken to improve the coverage.

Method and system for implementing graphical analysis of hierarchical coverage information using treemaps

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

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Raanana, Israel

Yaron Peri-Glass