Marvell Israel (misl) Ltd.

Neuroblade Ltd.

Yaron Kittner

Rami Zemach

Eliad Hillel

Nitzan Dror

Ilan Mayer-wolf

Yoav Markus

Gal Hai

Elad Sity

Ilan Yerushalmi

Adar Peery

Gideon Navon

Gal Dayan

Aviram Amir

Yaron Katzri

Oded Trainin

A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.

Read performance from disaggregated storage using distributed storage agents

A method for increasing accuracy of a timing protocol packet includes receiving, at a buffer of a first node, for transmission onto a transmission medium, at least one timing protocol packet among a plurality of packets, detecting that a delay-inducing phenomenon affecting a timestamp to be applied to a timing protocol packet will occur within a temporal interval, and in response to detecting that the delay-inducing phenomenon will occur within the temporal interval, preventing, during the temporal interval, application of the timestamp to the timing protocol packet and preventing transmission of the timing protocol packet onto the transmission medium until the delay-inducing phenomenon has elapsed.

Apparatus and method for preventing latency variation in timestamps of timing protocol packet transmitted through multi-lane ports

Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Data analysis acceleration architecture

Disclosed embodiments include a data filter system including an interface and data filter circuitry. The data filter circuitry is configured to receive a data filter initiation signal via the interface, and in response to receipt of the data filter initiation signal, perform at least one operation associated with a data query, wherein the data query implicates a body of data stored in at least one storage unit; wherein performance of the at least one operation associated with the data query results in generation of a filtered data subset from the body of data, including less data than the body of data implicated by the data query; and transfer the filtered data subset to a host processor configured to perform one or more additional operations relative to the data query to generate an output to the data query.

Inline data reduction

A network device provides a search key corresponding to a packet to a TCAM. The TCAM determines that the search key matches one or more search patterns stored in the TCAM. The network device selects one search pattern among the one or more search patterns at least by analyzing respective priority information associated with the one or more search patterns. The respective priority information indicates one or more respective priority levels that are independent from one or more physical locations of the one or more search patterns within the TCAM. In connection with selecting the one search pattern, the network device determines one or more actions to be performed on the packet by the network device, the one or more actions corresponding to the selected one search pattern.

Network device that utilizes TCAM configured to output multiple match indices

A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.

Hybrid fixed/programmable header parser for network devices

A network device includes a rate measurement circuit that is configured to measure respective egress rates at which respective data is being transmitted via respective ports associated with the network device. A marking ratio determination circuit is configured to select respective marking ratios based on respective measured egress rates, the marking ratios for marking packets to be transmitted via the respective ports to indicate respective levels of congestion corresponding to the respective ports. Different marking ratios correspond to different measured egress rates. A packet editor circuit is configured to mark selected packets to be transmitted via respective ports according to the respective selected marking ratios. The respective selected marking ratios indicate to other communication devices that respective network paths via which the selected packets travelled experienced congestion, and the respective marking ratios indicate respective levels of congestion.

Marking packets based on egress rate to indicate congestion

A network device comprises a network interface configured to transmit packets via a network link, and timestamp circuitry configured to modify a packet that is to be transmitted by the network interface circuitry by embedding a future timestamp in the packet. The future timestamp corresponds to a transmit time at which the packet is to be transmitted by the network interface circuitry, and the transmit time occurs after the timestamp circuitry embeds the timestamp in the packet. Time gating circuitry is configured to i) receive the packet, ii) determine when a current time indicated by a clock circuit reaches the transmit time, iii) hold the packet from proceeding to the network interface circuitry prior to the current time reaching the transmit time, and iv) release the packet in response to the current time reaching the transmit time.

Method and apparatus for transmit time timestamping

A network device includes a transmit buffer from which data is transmitted to a network, and a packet buffer from which data chunks are transmitted to the transmit buffer in response to read requests. The packet buffer has a maximum read latency from receipt of a read request to transmission of a responsive data chunk, and receives read requests including a read request for a first data chunk of a network packet and a plurality of additional read requests for additional data chunks of the network packet. A latency timer monitors elapsed time from receipt of the first read request, and outputs a latency signal when the elapsed time reaches the first maximum read latency. Transmission logic waits until the elapsed time equals the first maximum read latency, and then transmits the first data chunk from the transmit buffer, without regard to a fill level of the transmit buffer.

Network device having reduced latency

A network device for a communications network includes a port configured to transmit data to the network at a maximum transmit data rate. The device also includes a transmit buffer configured to buffer data units that are ready for transmission to the network, and a packet buffer configured to buffer data units before the data units are ready for transmission. The packet buffer is configured to output data units at a maximum packet buffer transmission rate faster than the maximum transmit data rate. The device includes a rate controller configured to control a transmission rate of data from the packet buffer to the transmit buffer so that averaged over a period, the transmission rate from the packet buffer to the transmit buffer is at most equal to the maximum transmit data rate, while allowing the transmission rate, at one or more time intervals, to exceed the maximum transmit data rate.

Network device having flexible rate limiter

A network device includes a transfer buffer having a plurality of memory banks, and a transfer buffer controller configured to perform a first number of write operations to write processed packets into a memory bank of the transfer buffer, monitor occupancy of the transfer buffer, and when occupancy of the transfer buffer is at least equal to a threshold, perform a predetermined number of read operations during each memory cycle, and when occupancy of the transfer buffer is less than the threshold, perform a second number of read operations, greater than the predetermined number, during each memory cycle. The device concurrently performs multiple read operations and multiple write operations in a single cycle using a plurality of ports. The buffer controller distributes data among the memory banks by allocating write addresses to keep memory occupancy substantially uniform among the memory banks, thereby freeing ports to allow performance of read operations.

Network device and method of operation

A network device includes: a set of content memory banks including a first memory bank; a parity memory bank; a first memory interface; and a second memory interface. The first memory interface is configured to perform a write operation to write new content data to a location in a first content memory bank in a plurality of partial write operations that are spread over two or more clock cycles, including: generating new parity information for the new content data using old content data at the location in the first content memory bank, and storing the new parity information to the parity memory bank. The second memory interface is configured to perform a read operation at the location in the first content memory bank concurrently while the first memory interface is performing at least one of the plurality of partial write operations.

System and method for performing simultaneous read and write operations in a memory

A memory comprises a set of content memory banks, a parity memory bank, and a register corresponding to the parity memory bank. A first memory interface device is configured to, in response to receiving a write request to write to the set of content memory banks, perform a write operation over multiple clock cycles including temporarily storing parity information corresponding to the write request in the register before the parity information is written to the parity memory bank. A second memory interface device is configured to: in response to i) receiving a read request to read data from a memory bank in the set of content memory banks, and ii) determining that information responsive to the read request is to be reconstructed using parity information, and selectively use information from either i) the register or ii) the parity memory bank, to reconstruct information responsive to the read request.

Growing community of inventors

Pardes Hanna-Karkur, Israel

Yaron Kittner