Verisity, Ltd.

Cadence Design Systems, Inc.

Cadence Design (israel) II Ltd.

Yaron Kashai

Yoav Z Hollander

Matthew John Morley

Gilad Bracha

Felice Balarin

Neyaz Khan

John Paul Decker

Stavros Tripakis

Lev Plotnikov

Efrat Shneydor

A method for identifying an anomaly in an electronic system includes receiving, from a computer-readable storage medium, a plurality of entries from a successful simulation test of the electronic system, each of the plurality of entries including information about simulation time. The method also includes, with one or more computer processors, determining time sequence relationship between pairs of entries selected from the plurality of entries and identifying allowable sequences of entries using information related to the first plurality of entries and the time sequence relationship. The method includes receiving a second plurality of entries from a failed simulation test of the electronic system, each of the second plurality of entries including information about simulation time. The method includes analyzing the second plurality of entries and identifying one or more anomalies in the electronic system based on the analysis of the failed simulation test.

Automatic anomaly detection for HW debug

The present disclosure relates to a computer-implemented method for automatically generating a power management verification component. The method may include receiving one or more inputs including a power intent definition. The method may further include automatically generating a power management verification environment based upon, at least in part, the power intent definition, the power management verification environment including at least one of a driver and a monitor.

System, method, and computer program product for automatic power management verification

Disclosed are a method, system, and computer program product for implementing external domain independent modeling framework in a system design. In some embodiments, the method or system comprises importing an external model in an external format into the framework while substantially preserving some or all of the interpretation of the external model, determining a internal common representation for the external model within the framework, and displaying or storing the internal common representation in a tangible computer readable medium. In some embodiments, the method or system further comprises validating the accuracy of the internal common representation, determining an analysis or transformation capability for the framework, or outputting a first output model in a second external format. In various embodiments, the method or system requires no external tool compliance.

Method, system, and computer program product for implementing external domain independent modeling framework in a system design

Disclosed are a method, a system, and a computer program products for implementing model exchange in a system design. In various embodiments, the method or system receives a model exchange request from a client where model exchange request comprises a first synchronization record which comprises a delta of both a program aspect and a data aspect between a system design on the client and a system design on the server, implements the first model exchange request by processing the first model exchange, generates a second synchronization record in response to the first model exchange, transmitting the second synchronization record to the first client by using a fusion technology, and displaying a result of implementing the first model exchange request or storing the result in a tangible computer readable medium.

Method, system, and computer program product for implementing a model exchange framework generating a synchronization record in response to a model exchange request using fusion technology

A system and method for generalized scenarios, for automatically generating tests. The tests are generated from some underlying structure, such as one or more scenarios. The scenarios preferably include a plurality of constraints for generating a test program for generating input values to the test generation process. The scenarios provide a more generalized method for generating tests.

Method and system for automatically creating tests

Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT using a constraint-based random test generation process. For example, the architecture, structure, and/or content of the verification test data may be defined in response to constraint data and an input/output data model. A first portion of the verification test data is applied to the physical DUT. Output data is captured from the physical DUT in response to application of the first portion of the verification test data. A second portion of the verification test data is selected in response to the output data. Expected output data for the physical DUT associated with the verification test data may be generated and compared with the output data captured from the DUT to functionally verify the design of the DUT.

Method and apparatus for functionally verifying a physical device under test

A system and method for enabling the behavior of temporal expressions to be analyzed for the evaluation of such expressions. The process of evaluating such expressions ultimately results in the construction of a finite state machine, such that the set of non-deterministic functions for describing the behavior of dynamic and relativistic systems is reduced to such a system. The behavior of the finite state machine can then be examined and analyzed. The present invention is useful for such applications as the examination of the temporal behavior of a DUT (device under test), as well as for examining the behavior of dynamic systems.

System and method for compiling temporal expressions

A method for synthesizing a verification language, and thereby enabling the verification language to be compiled into a target language. This method enables the underlying control structure of the verification language to be determined, and then used to map the dynamic behavior of the verification language onto the target language as part of a static framework. The process of synthesizing any type of verification language causes at least a portion of the implicit control structure of the software program to be constructed into the compiled output code, such that an additional scheduler or other type of runtime system may not be required. Therefore, the compiled output code should have a greater execution speed and should be operated more efficiently than the software programs which are written in the verification language itself.

Synthesis of verification languages

A system and method for testing the quality of a simulation model for the DUT (device under test) through temporal coverage of the testing and verification process. Temporal coverage examines the behavior of selected variables over time, according to a triggering event. Such a triggering event could be determined according to predefined sampling times and/or according to the behavior of another variable, for example. This information is collected during the testing/verification process, and is then analyzed in order to determine the behavior of these variables, as well as the quality of the simulation model for the DUT. For example, the temporal coverage information can be analyzed to search for a coverage hole, indicated by the absence of a particular value from a family of values.

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Sunnyvale, CA, United States of America

Yaron Kashai