Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

Taiwan China Company, Limited

Yaqi Ma

Lei Pan

Wei Yu Li

JunKui Hu

Yongliang Jin

Jing Ding

CunCun Chen

XinYong Wang

Zhang-Ying Yan

Kai Zhou

MingJian Wang

JiaLiang Zhong

A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Integrated circuit and method of manufacturing same

A method of manufacturing an IC structure includes forming first through fourth PMOS transistors in an n-well, constructing a bias circuit including the first and second PMOS transistors, constructing a level shifter including the third and fourth PMOS transistors, building a first power distribution structure including electrical connections to each of the first and third PMOS transistors, and building a second power distribution structure including electrical connections to each of the second and fourth PMOS transistors.

Level shifting circuit manufacturing method

A circuit (to shape a follower voltage for a follower circuit) includes a tie-low circuit and an anti-noise circuit. The tie-low circuit is connected between a follower node and a first reference voltage. The tie-low circuit is responsive to a second reference voltage. The follower node is connectable to the follower circuit. The anti-noise circuit is connected between the follower node and the second reference voltage. The anti-noise circuit is configured to protect the follower voltage at the follower node from otherwise being distorted by a noise voltage being coupled capacitively to the follower node.

Semiconductor circuit including a tie-low circuit and method of fabricating same

An integrated circuit (IC) device includes a first substrate, a through substrate via (TSV) in the first substrate, and a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV. The first antenna effect protection circuit includes at least one first transistor of a first type, and at least one second transistor of a second type different from the first type. A gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.

Integrated circuit device with antenna effect protection circuit and method of manufacturing

An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Level shifting circuit and method

A circuit includes an output node and an amplifier and first and second branches coupled between power supply and reference nodes. The first branch includes a first switching device coupled between a first amplifier input and the reference node, the second branch includes a second switching device coupled between the output node and a second amplifier input, and a third switching device is coupled between the power supply and output nodes. Responsive to a first voltage level on the power supply node, each of the first and second switching devices is switched off and the third switching device is switched on, and responsive to a second voltage level on the power supply node greater than the first voltage level, each of the first and second switching devices is switched on and the third switching device is switched off.

Dual mode supply circuit and method

A circuit includes a first passive device between supply and bias nodes, a first switching device and a second passive device between the bias and a reference node, a transistor between the supply and an output node, a third passive device and a second switching device between the output and a feedback node, a fourth passive device between the feedback and reference nodes, a third switching device between the supply and output nodes, and an amplifier controlling the transistor based on bias node and feedback node voltages. In a first mode, the first and second switching devices are off, the third switching device is on, and the supply node receives a first voltage level. In a second mode, the first and second switching devices are on, the third switching device is off, and a second voltage level greater than the first voltage level is received on the supply node.

A circuit includes a bias circuit and a level shifter. The bias circuit includes first and second input terminals configured to receive first and second power supply voltages, and is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a bulk terminal configured to receive the bias voltage.

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Hsinchu, Taiwan

Yaqi Ma