Texas Instruments Corporation

Vitesse Semiconductor Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Yaqi Hu

Yanli Fan

Huawen Jin

Mark William Morgan

Jawaid Ahmad

Ulrich Schacht

Dave Bergman

Kok-Lean Tan

Karl Muth

Jim McDonald

Driving a back-gate of a transistor with a follower signal that corresponds to an information signal. At least some of the illustrative embodiments are methods including: passing an information signal from a drain terminal to a source terminal of a main field effect transistor (FET), the information signal has a peak-to-peak voltage; generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; and applying the follower signal to a back-gate of the main FET.

Transistor switch with back-gate biasing

An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.

Adaptive real-time control of de-emphasis level in a USB 3.0 signal conditioner based on incoming signal frequency range

An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Linear system for link training

In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower electrostatic discharge (ESD) performance. Here, a mixed or hybrid mode driver is provided that employs a current steering circuit (instead of voltages driven differential pair(s) as is done with conventional drivers) to generate pull-down currents that precisely match the voltages in the pull-up portions of driver. It increases the speed and produces smaller output common-mode voltage fluctuation over conventional drivers. Thus, the driver provided here can be produced in BiCMOS process technologies without the undesirable effects of conventional drivers.

Low-power high-speed differential driver with precision current steering

In the many microelectronics applications, delays present in circuitry can affect both the design and the function of the circuitry. One example of delays impacting the function of a circuit is a relaxation oscillator, where delays present in comparator circuits and latches can cause its frequency to vary beyond desired ranges. Here, a relaxation circuit with delay compensation is described.

Oscillator with delay compensation

The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to a node to be compensated; a first resistance coupled between an output of the amplifier and the replica circuit; a second resistance coupled between the output of the amplifier and the node to be compensated; and wherein the replica leakage current is subtracted from the node to be compensated.

Leakage compensation circuit using limiting current inverter

A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Clock buffer with DC offset suppression

Methods and apparatus for providing precision on-chip termination of transmission lines are provided which enable the termination of transmission lines using on-chip resistors configured into networks, which have resistances related to the resistance of an external reference resistor. The external reference resistor is used to configure an on-chip reference resistor network so that it has a resistance related to the resistance of the external reference resistor. Termination resistor networks are then configured so that their resistances bear a predetermined relationship to the resistance of the on-chip reference resistor network. In one embodiment the resistance of each of the termination resistor networks is substantially the same as the characteristic impedances of each of the transmission lines.

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Plano, TX, United States of America

Yaqi Hu