Aptina Imaging Corporation

Omnivision Technologies, Inc.

Smartsens Technology (cayman) Co., Limited

Smartsens Technology (hk) Co, Limited

Smartsens Technology (us) Inc.

Smartsense Technology (u.s.) Inc.

Yaowu Mo

Chen Hui Xu

Zexu Shao

Weijian Ma

Zhengmin Zhang

Guanjing Ren

Min Qu

Yandong Chen

Tiejun Dai

Rui Wang

Xiaodong Luo

Xiao Xie

Jinjian Hou

Wenjie Shi

Yue Ping Li

Joseph W Yang

Guangbin Zhang

Donghui Wu

Xiaoyong Wang

Eiichi Funatsu

Wei Wang

Zhibin Xiong

Ko Ping Keung

Zhengyu Li

Shaomin Ding

Mei Yan

Weijan Ma

Xuanping Zhou

Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel has a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Pixel unit with a design for half row reading, an imaging apparatus including the same, and an imaging method thereof

An image sensor pixel noise suppression circuit having a source follower transistor based pixel circuit, a power supply voltage and noise mirror circuit, a power supply voltage and noise gain circuit, and a comparator circuit. An output of the comparator circuit provides an image related output signal wherein the noise component of the source follower signal has been suppressed. The invention further includes a CMOS image sensor containing the image sensor pixel noise suppression circuit.

CMOS image sensor with pixel power supply noise suppression circuit

An image sensor array and circuit design employs a method of black level compensation to address vertical image shading related to global exposure image capture and rolling row by row readout schemes. An image sensor having the invented black level compensation pixel array and method may be incorporated within a digital camera.

CMOS image sensor with image black level compensation and method

Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel comprises a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

A pixel cell and row select and row driver circuits include two column bias circuits and row driver circuits, one placed at the right and one placed at the left side of the array of pixel cells. The digital control signals for the two sets of bias and row driver circuits enter at the center top or bottom of the array of pixel cells and drive the circuits symmetrically. The combination of two-sided row driver and column bias helps eliminate any signal delay and bias difference between the left and right side of the pixel cell array. More significantly this circuit construction can minimize horizontal shading in the resulting image.

Dual row control signal circuit for reduced image sensor shading

An improved DNA sequencing system comprising a DNA sample holder residing on a stacked BSI global shutter image sensor illuminated by a pulsed laser for fluorescent illumination detection. The pulsed laser has on and off periods wherein during the laser on period a Fluorophore tag attached to a DNA sample is excited to produce fluorescence emission while the imaging system captures no illumination and during the off period the global shutter imaging system captures persistent fluorescent emission from the DNA sample and reads out an imaging signal.

DNA sequencing system with stacked BSI global shutter image sensor

An imaging sensor having a pixel array with a separate analog-to-digital conversion (ADC) circuit coupled on an input side to each column line and on an output side to a separate M-bit wide digital memory circuit and a column data readout circuit comprising N M-bit data shifters. Each M-bit data shifter has an M-bit wide output, and single pole double throw (SPDT) switches whose common terminals provide inputs to the M-bit data shifters, wherein a first switch state of the SPDT switches connects the input of their associated M-bit data shifters to their associated M-bit wide digital memory circuits and wherein a second switch state of the SPDT switches connects the input of their associated M-bit data shifters to an M-bit wide output bus from an adjacent M-bit data shifter.

CMOS image sensor with improved column data shift readout

A pixel cell and readout circuit includes an anti-eclipse voltage clamp circuit at both the top and bottom of each column line of an array of the pixel cells. The anti-eclipse voltage clamp circuits form a row with each column in the array coupled to an anti-eclipse voltage clamp circuit. The combination of two rows of anti-eclipse voltage clamp circuits helps settle the clamp voltage more rapidly and to compensate for the increased length of the anti-eclipse voltage circuit row as well as the column line resistance due to narrow metal lines and increased numbers of pixels as well as the requirement to operate a sensor at a higher frame rate. More significantly this circuit construction can minimize vertical shading in the resulting image.

Dual eclipse circuit for reduced image sensor shading

A pixel cell has a large and small photodiode, transfer transistors, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, a storage capacitor, a storage capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The small and large photodiodes are exposed simultaneously, the large photodiode having a constant exposure while the small photodiode has a chopped exposure and charge transfer to a storage capacitor.

Wide dynamic range image sensor pixel cell

An image sensor has a pixel cell array comprising clusters of pixel cell blocks each block having four pixel cells under the same microlens and filter wherein during readout electrical signals from two pixels positioned along a first diagonal are binned followed by binning the signals from two pixels positioned along the remaining second reverse diagonal in order to reduce spatial color artifacts associated with orthogonal binning schemes and minimize gaps or irregular spacing between optical centers within an image read out from the array of pixel cells.

HDR pixel array with double diagonal binning

An image sensor has global shutter imaging pixel cells, each including an anti-blooming transistor gate for modifying electric charge within a photodiode and for setting the photodiode to a selected potential. The sensor also has a row decoder circuit providing readout signals to each row of the imaging cells during both a readout interval and during a calibration interval for each row and providing to the anti-blooming transistor drain a selectable potential supply voltage. A mode select switch within the row decoder circuit applies either a standard drain supply voltage or an adjustable low voltage to the anti-blooming transistor drain. A programmable function logic circuit determines the timing of operation of the mode select switch to provide knee-point calibration to minimize photo conversion variations that lead to fixed pattern noise.

Global shutter image sensor with anti-blooming pixel and knee point self-calibration

An image sensor has a stacked pixel arrangement including both rolling and global shutter readout circuits wherein each pixel includes an adjustable transfer transistor gate voltage level for modifying electric charge within a photodiode during exposure depending on incident light intensity. The sensor also has a row decoder circuit providing readout signals to each row of the imaging cells during both a readout interval and during a calibration interval for each row. The row decoder may employ one of several of its features to provide a self-knee point calibration following an image signal readout in order to minimize photo conversion variations that lead to fixed pattern noise and to enhance dynamic range.

Stacked rolling shutter and global shutter image sensor with knee self point calibration

A pixel cell has four maskless phase detection photodiodes sharing the same readout amplifier, microlens and filter color. The four photodiodes are configured to operate in two adjacent pairs wherein the two adjacent pairs of photodiodes are separated by a light guide and are positioned under the single microlens such that light incident in a first direction is collected in a first pair of photodiodes of the two adjacent pairs of photodiodes and light incident in a second direction is collected in a second pair of photodiodes of the two adjacent pairs of photodiodes. The microlens has a plano-convex shape which causes light to be incident in two directions on photodiodes positioned under each of two sides of the microlens.

Four shared pixel with phase detection and full array readout modes

A pixel cell has a photodiode, a transfer transistor, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The photodiode, a transfer transistor, a reset transistor, dynamic range enhancement capacitor, capacitor control transistor, amplifier transistor and rolling shutter row select transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Stacked image sensor pixel cell with dynamic range enhancement and selectable shutter modes and in-pixel CDS

A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor and a readout circuit block. The photodiode, transfer transistor, reset transistor and amplifier transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode and converting the image charge to an image signal. The readout circuit block is disposed within a second substrate of a second semiconductor chip and the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

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San Ramon, CA, United States of America

Yaowu Mo