Ansys, Inc.

Yaowei Jia

Xiaoqin Liu

Sooyong Kim

Wenliang Zhang

Norman H Chang

Joao Moreno Geada

Ying-Shiun Li

Sankar Ramachandran

Hao Zhuang

Rahul Rajan

Mathew Joseph Kaipanatu

Suresh Kumar Mantena

Ganesh Tsavatapalli

Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.

Double glitch capture mode power integrity analysis

Example systems and methods are disclosed for performing a timing analysis on a circuit design. A plurality of switching scenarios are identified for the circuit design. One or more predictive models are applied to predict a subset of the plurality of switching scenarios that are likely to cause timing paths with critical timing problems. A dynamic voltage analysis is performed on timing paths based on the subset of switching scenarios. The one or more predictive models are applied to predict a set of critical timing paths based on the subset of switching scenarios that are likely to cause critical timing problems, the one or more predictive models taking into account the dynamic voltage analysis. A timing analysis is the performed on the set of critical timing paths.

Timing assistant for dynamic voltage drop impact on setup/hold constraints

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San Jose, CA, United States of America

Yaowei Jia