Ningbo University

Yaopeng Kang

Pengjun Wang

Daohui Gong

Huihong Zhang

Yuejun Zhang

A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1CNFET transistor, the 2CNFET transistor, the 3CNFET transistor, the 4CNFET transistor, the 5CNFET transistor, the 6CNFET transistor, the 7CNFET transistor, the 8CNFET transistor, the 9CNFET transistor, the 10CNFET transistor, the 11CNFET transistor, the 12CNFET transistor and the 13CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1inverter, the 2inverter, the 3inverter, the 4inverter, the 14CNFET transistor, the 15CNFET transistor, the 16CNFET transistor, the 17CNFET transistor, the 18CNFET transistor and the 19CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Ternary sense amplifier and SRAM array realized by the ternary sense amplifier

The present invention discloses a ternary 2-9 line address decoder realized by CNFET, comprising two ternary 1-3 line address decoders of the same structure, nine three-input NAND gates of the same structure and nine inverters of the same structure; the ternary 1-3 line address decoder comprises a 1CNFET transistor, a 2CNFET transistor, a 3CNFET transistor, a 4CNFET transistor, a 5CNFET transistor, a 6CNFET transistor, a 7CNFET transistor, an 8CNFET transistor, a 9CNFET transistor, a 10CNFET transistor and an 11CNFET transistor; as compared with a 3-8 line address decoder, it features in limited deviation to an output terminals and significant reduction in the number of input terminals, which can minimize the number of ports as packaging, and improve decoding efficiency; furthermore, it is realized by CNFET, which features in low power consumption and less postponement.

Ternary 2-9 line address decoder realized by CNFET

The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF circuit is arranged into a 3rows&#xd7;3columns matrix formed by 3&#xd7;3ternary PUF units; the ternary PUF unit comprises a 1CNFET transistor, a 2CNFET transistor, a 3CNFET transistor, a 4CNFET transistor, a 5CNFET transistor, a 6CNFET transistor, a 7CNFET transistor, an 8CNFET transistor, a 9CNFET transistor and a 10CNFET transistor; its advantage lies in the fact that it is provided with small circuit area and higher randomness and uniqueness while ensuring proper logic function.

Growing community of inventors

Zhejiang, China

Yaopeng Kang