Lattice Semiconductor Corporation

Maxim Integrated Products, Inc.

Synopsys, Inc.

Yaohua Yang

James Lawrence Gorecki

Hans W Klein

Benjamin J McCarroll

Jian Li

Ruoxin Jiang

Rumin Yin

David A Martin

Bill G Gazeley

An electronic device comprising a matched filter to drive a LED module is disclosed. The matched filter receives an incoming rectangular pulse and outputs a modulated driving signal to drive the LED module. The optical output from the LED is captured by an optical sensor and converted to electrical signal for analysis. A decimation filter couples to the optical sensor in an effort of reducing sampling rate and quantization noise of the converted electrical signal. The modulated driving signal output from the matched filter keeps the LED current, thus LED light, matching the time-mirrored impulse response of the decimation filter to obtain or approach a theoretical maximum signal-to-noise (SNR) at a fixed amount of power.

Matched filter techniques configured to fire led using a sloped response

The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs an automatic slicer level adaption to enhance the performance of a high speed communications system.

System and method for providing slicer level adaption

A frequency-to-current converter operative to convert a clock frequency to an output current is described; the frequency-to-current converter ensures that the output current increases linearly with the clock frequency. The frequency-to-current converter may be incorporated in analog-to-digital converters driven by clocks with variable frequencies. The frequency-to-current converter employs an integrator circuit, used to compare an input reference voltage and a current feedback into a sampling capacitor. At steady state, the feedback current is just sufficient to discharge the sampling capacitor to a fixed voltage. The core of the frequency-to-current conversion circuit includes one opamp, two capacitors, one feedback transistor and a few switches.

Switched-capacitor frequency-to-current converter

A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.

Integrated programmable continuous time filter with programmable capacitor arrays

A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weighted sum of input signals to the floating gates of the first comparator stage. Additionally, the double differential comparator can be integrated into fully differential programmable analog integrated circuits. Such fully differential programmable analog integrated circuits can also include a differential output digital-to-analog converter to be used with or without the double differential comparator.

Double differential comparator and programmable analog block architecture using same

A composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.

Offset voltage calibration DAC with reduced sensitivity to mismatch errors

Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

Amplifier having an adjust resistor network

A CMOS programmable resistor-based transconductor receives a differential input voltage and generates a differential output current. The transconductor includes a degenerate pair of transistors linearized by servo feedback, and further includes a string of series-connected resistors defining a group of tap points. Two selected tap points in the resistor string are selected by digital control of MOS switches and are connected, respectively, to the feedback input of the two amplifiers in the feedback loops. Because no DC current flows through the MOS switches into the high impedance inputs of the amplifiers, the differential input voltage is impressed across a portion of the resistor string residing between the two selected tap points, and the conversion gain is determined by the value of this portion of the resistor string.

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West Linn, OR, United States of America

Yaohua Yang