Innoscience (Zhuhai) Technology Co., Ltd.

Innoscience (Suzhou) Semiconductor Co., Ltd.

Yaobin Guan

Jianjian Sheng

Junyuan Lv

Zhenzhe Li

A semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.

Clamping circuit integrated on gallium nitride semiconductor device and related semiconductor device

The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

Electrostatic protection circuit and electronic device

An electronic device includes a first group III nitride transistor and an over current protection circuit (OCP). The OCP circuit includes an input device and a detection device. The input device is configured to receive a control signal and to generate a first voltage to a gate of the first group III nitride transistor. The detection device is configured to generate an output signal having a first logical value if a current at a drain of the first group III nitride transistor is less than a predetermined value and to generate the output signal having a second logical value if the current at the drain of the first group III nitride transistor is equal to or greater than the predetermined value, wherein the first logical value is different from the second logical value.

Electronic device and over current protection circuit

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

Electronic device and electrostatic discharge protection circuit

The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.

Growing community of inventors

Zhuhai, China

Yaobin Guan