Yangtze Memory Technologies Co., Ltd.

Yaobin Feng

Zhiliang Xia

Qingchen Cao

Zongliang Huo

Fandong Liu

Baoyou Chen

Jia He

Peizhen Hong

Yaohua Yang

Haihui Huang

Zi Qun Hua

Lu Ming Fan

Bi Feng Li

ZongLiang Huo

Jun He

Zhi Hu Gao

Dou Dou Zhang

Jin Yu Qiu

Zhi Yang Song

Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Openings layout of three-dimensional memory device

A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Method and structure for cutting dense line patterns using self-aligned double patterning

Systems and methods for evaluating critical dimensions of a semiconductor device are provided. The semiconductor device includes a first layer comprising a first set of overlay markings and a second layer comprising a second set of overlay markings. The second layer is higher than the first layer. The first set of overlay markings includes a plurality of diffraction gratings. Each of the plurality of diffraction gratings has a first period. The second set of overlay markings includes a plurality diffraction grating clusters. Each of the plurality of diffraction grating clusters has a plurality of diffraction grating units. The plurality of diffraction grating units in at least one of the plurality of diffraction grating clusters have the first period. At least one of the plurality of diffraction grating units includes a diffraction grating having a second period that is smaller than the first period.

Systems and methods for evaluating critical dimensions based on diffraction-based overlay metrology

Systems and methods for evaluating critical dimensions of a semiconductor device are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include receiving information of a first set of overlay markings on a first layer of the semiconductor device and information of a second set of overlay markings on a second layer of the semiconductor device. The first layer is lower than the second layer. The operations also include receiving a plurality of diffraction parameters measured from corresponding overlay markings on the first and second layers. The operations further include determining a variation of the critical dimensions on the second layer based on the plurality of diffraction parameters.

Embodiments of semiconductor fabrication methods are disclosed. In an example, a method for forming a mark for locating patterns in semiconductor fabrication is disclosed. A wafer is divided into a plurality of shots. Each of the plurality of shots includes a semiconductor chip die. Four quarters of a locking corner mark are subsequently patterned, respectively, at four corners of four adjacent shots of the plurality of shots. Each quarter of the locking corner mark is symmetric to adjacent quarters of the locking corner mark and is separated from the adjacent quarters of the locking corner mark by a nominally same distance. The locking corner mark is set as an origin for locating patterns in at least one of the four adjacent shots in semiconductor fabrication.

Marks for locating patterns in semiconductor fabrication

Growing community of inventors

Hubei, China

Yaobin Feng