Mstar Semiconductor, Inc.

Yao-Zhong Zhang

Chun-Chia Chen

Hsian-Feng Liu

Chih-Tien Chang

Jian-Feng Shiu

Ju-Ming Chou

Hsin-Kuang Chen

A signal transmission method suitable for DDR for driving a connecting pad includes a level shifting circuit including up and down level shifters, a buffer circuit including up and down buffer units, and an output circuit. The level shifting circuit, disposed between a DDR operating voltage and a ground voltage, receives an input signal in a first operating voltage equal to the ground voltage and a second operating voltage smaller than the DDR operating voltage. The up buffer unit is disposed between the DDR operating voltage and a first reference voltage, and the down buffer unit is disposed between the ground voltage and a second reference voltage equal to the second operating voltage. The up and down level shifters adopt IO devices, and other components adopt core devices. The first reference voltage is a difference between the DDR operating voltage and the second reference voltage.

Signal transmission circuit suitable for DDR

An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage.

Input/output circuit with high voltage tolerance and associated apparatus

An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.

Growing community of inventors

Shanghai, China

Yao-Zhong Zhang