International Business Machines Corporation

Yao Yao

Ruilong Xie

Veeraraghavan S Basker

Andrew Mark Greene

Alexander Reznicek

Devendra K Sadana

Ning Li

Joel Pereira De Souza

Kangguo Cheng

Zhenxing Bi

Jingyun Zhang

Reinaldo Ariel Vega

Robert Russell Robison

Yun Seog Lee

Pietro Montanini

A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

Wraparound contact with reduced distance to channel

A semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a bottom source/drain (S/D) region directly contacting a bottom surface of the first and second set of fins, and a top S/D region directly contacting a top surface of the first and second set of fins. A high-k metal gate (HKMG) is disposed between fins of the first set of fins and between fins of the second set of fins. The HKMG directly contacts sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.

Vertical FET replacement gate formation with variable fin pitch

A method is presented for forming a wrap around contact. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, forming a dielectric pillar between the p-type epitaxial region and the n-type epitaxial region, depositing sacrificial liners around both the p-type epitaxial region and the n-type epitaxial region, and depositing an inter-layer dielectric (ILD). The method further includes forming trenches in the ILD extending into the sacrificial liners, wherein the trenches are vertically aligned with the p-type epitaxial region and the n-type epitaxial region, removing the sacrificial liners to define irregular-shaped openings exposing the p-type epitaxial region and the n-type epitaxial region, and filling the irregular-shaped openings with a conductive material defining the wrap around contact.

Wrap around contact process margin improvement with early contact cut

Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.

Dual step etch-back inner spacer formation

A method for manufacturing a semiconductor device includes forming a plurality of first semiconductor layers alternately stacked with a plurality of second semiconductor layers on a semiconductor substrate, and laterally recessing the plurality of first semiconductor layers with respect to the plurality of second semiconductor layers to form a plurality of vacant areas on lateral sides of the plurality of first semiconductor layers. In the method, a plurality of first inner spacers are formed on the lateral sides of the plurality of first semiconductor layers in respective ones of the plurality of vacant areas, and a plurality of second inner spacers are formed on sides of the plurality of first inner spacers in the respective ones of the plurality of vacant areas. The method also includes laterally recessing the plurality of second semiconductor layers, and growing a plurality of source/drain regions from the plurality of second semiconductor layers.

Protective bilayer inner spacer for nanosheet devices

A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.

Source and drain EPI protective spacer during single diffusion break formation

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

Photodetector having a tunable junction region doping profile configured to improve contact resistance performance

A semiconductor device is formed using an n-type layer of Zinc Oxide, a p-type layer formed of a narrow bandgap material. The narrow bandgap material uses a group 3A element and a group 5A element. A junction is formed between the n-type layer and the p-type layer, the junction being operable as a heterojunction diode having a rectifying property at a temperature range, the temperature range having a high limit at room temperature.

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Albany, NY, United States of America

Yao Yao