Macronix International Co., Ltd.

Yao Wen Chang

Tao Cheng Lu

Wen Jer Tsai

I Chen Yang

Tao-Cheng Lu

Po Chou Chen

Hui Chih Lin

Guan Wei Wu

Chu Yung Liu

Hsin Wen Chang

Hsing Wen Chang

A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.

Semiconductor structure

A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.

Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme

A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells.

Window enlargement by selective erase of non-volatile memory cells

A high-voltage semiconductor device includes a silicon substrate having a main surface, a gate on the main surface of the silicon substrate, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. A channel region is defined in a portion of the silicon substrate proximate the main surface between the source region and the drain region. The channel region is at least partially beneath the gate. An additional region is disposed on the main surface proximate the channel region. The additional region being formed of one of a high-k material and a conductive material.

High voltage device

A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.

NROM structure

A MOSFET structure comprises a tortuous gate having a first sidewall and a second sidewall, disposed over a semiconductor substrate. A source region is disposed within the semiconductor substrate adjacent to the first sidewall of the tortuous gate. The source region comprises a broader part and a narrower part. Contacts are positioned above the broader part of the source region and are in contact with the broader part of the source region. A drain region is disposed within the semiconductor substrate adjacent to the second sidewall of the tortuous gate. The drain region comprises a broader part and a narrower part. Contacts are disposed above the broader part of the drain region and are in contact with the broader part of the drain region. The broader part of the drain region is disposed opposite to the narrower part of the source region. The narrower part of the drain region is disposed opposite to the broader part of the source region.

MOSFET structure with reduced junction capacitance

A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.

Growing community of inventors

Hsinchu, Taiwan

Yao Wen Chang