Taiwan Semiconductor Manufacturing Comp. Ltd.

Hon Hai Precision Industry Co., Ltd.

Anaglobe Technology, Inc.

Other

Synopsys, Inc.

National Taiwan University

Springsoft, Inc.

Springsoft Usa, Inc.

International Business Machines Corporation

Mediatek Corporation

National Yang Ming Chiao Tung University

Chang Gung University

Yao-Wen Chang

Cheng-Yuan Tsai

Hsing-Lien Lin

Jian-Shiou Huang

Chia-Shiung Tsai

Chia-Hua Lin

Hai-Dang Trinh

Hsun-Chung Kuang

Tzu-Yu Lin

Tzu-Chung Tsai

Tsung-Hsueh Yang

Chia-Wen Zhong

Shih-Chang Liu

Chern-Yow Hsu

Sheng-Chau Chen

Chung-Yen Chou

Fu-Ting Sung

Gung-Pei Chang

Kong-Beng Thei

Yen-Liang Lin

Meng-Kai Hsu

Cheng-Tai Hsiao

Yu-Tsang Hsieh

Chii-Ming M Wu

Yuan-Tai Tseng

Hung Cho Wang

Sheng-Huang Huang

Chung-Chiang Min

Yen-Chang Chu

Tung-Chieh Chen

Pei-Wen Hsieh

Ching-Ping Tseng

Harry-Hak-Lay Chuang

Kai-Wen Cheng

Yu-Hsing Chang

Chun-Yi Yang

Eugene I-Chun Chen

Ching-Sheng Chu

Chih-Che Lin

Shyh-Chang Lin

Hsien-Shih Chiu

Tien-Chang Hsu

Po-Wei Lee

I-Jye Lin

Shih-Chun Chen

Chao-Hung Wang

Yu-Sheng Lu

Chen-Feng Chang

Chin-Fang Shen

Chun-Wei Lin

Julie Yang

Yen-Yi Wu

Alexander Kalnitsky

Gi-Joon Nam

Ru-Liang Lee

Gustavo Enrique Tellez

Han-Chin Chiu

Chin-Wei Liang

Bi-Shen Lee

Kuo-Liang Lu

Ming-Wei Tsai

Min-Chang Ching

Cheng-Te Lee

Tien-Yueh Liu

Chern-yow Hsu

Jui-Lin Chu

Ching Ju Yang

Huan-Chieh Chen

Wen-Yuan Hsieh

Jinwook Jung

Kai-Yu Yang

Hua-Yu Chang

Yu-Ling Huang

Hui-Ru Jiang

Jennifer Kazda

Hsiang-Wen Chang

Kai-Han Tseng

Bo-Qiao Lin

Ting-Chou Lin

I-Peng Wu

Hung-Chih Ou

Sheng-Jung Yu

Shin-Hsin Hsu

Valeriy Balabanov

Ping-Hung Yu

Fwu-Juh Huang

Xin-Wei Shih

Tai-Chen Chen

Feng-Yuan Chang

Chau-Chin Huang

Min-Hsuan Chung

Yan-Lin Chen

Kuan-Cheng Chen

Ping-Wei Huang

Ching-sheng Chu

Chii Ming Wu

Yang Hsu

Chun-Han Chiang

Fu-Yu Chuang

Embodiments are provided for providing enhanced fabrication and design of an integrated circuit in a computing system by a processor. One or more latches may be clustered by augmenting an integer linear program ('ILP') operation with a facility-location allocation (FLA) operation, wherein the clustering of the one or more latches is timing-aware. The one or more latches may be placed and assigned in the integrated chip based on clustering one or more latches.

Timing-aware and simultaneous optimization of latch clustering and placement in an integrated circuit

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

Ferroelectric memory device and method of fabricating the same

A method, a system, and non-transitory computer readable medium for power and ground (P/G) routing for an integrated circuit (IC) design are provided. The method includes generating input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design, and modifying a set of P/G vias or a set of P/G wires in the P/G network according to modifications identified by the ML model. The ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.

Machine-learning-based power/ground (P/G) via removal

In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

Hard mask layer below via structure in display device

A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.

MIM capacitor and method of forming the same

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Integrated chip including an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.

Film scheme to reduce plasma-induced damage

. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

Bottom-electrode interface structure for memory

A semiconductor structure includes a bottom electrode, a magnetic tunneling junction stack over the bottom electrode, a top electrode over the magnetic tunneling junction stack, a first dielectric layer under the bottom electrode, a second dielectric layer under the first dielectric layer. The first dielectric layer has a first chemical bond energy and the second dielectric layer has a second chemical bond energy less than the first chemical bond energy.

Semiconductor structure and method of manufacture

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

Spacer film scheme form polarization improvement

A method of warpage-aware floorplanning for heterogeneous integration structure is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a performing a layout partitioning to divide a layout into a plurality of grids; performing an initial floorplanning by assigning first geometric relations between a plurality of dies such that an effective material of each grid of the plurality of grids is determined; performing a global floorplanning to change the first geometric relations between the plurality of dies to second geometric relations to optimize warpage effect of the heterogeneous integration structure; and performing a detailed floorplanning to determine die order of placement based on material differences between the plurality of dies and an interposer.

Method of warpage-aware floorplanning for heterogeneous integration structure

A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Capacitor structure and method of making the same

Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Sidewall spacer structure for memory cell

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Film structure for bond pad

A semiconductor structure includes an Nmetal layer, a diffusion barrier layer over the Nmetal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Semiconductor structure, electrode structure and method of forming the same

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Taipei, Taiwan

Yao-Wen Chang