Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Yao-Min Liu

Hung-Wen Su

Shu-Cheng Chin

Chih-Chien Chi

Chia-Pang Kuo

Chun-Chieh Lin

Ya-Lien Lee

Chi-Feng Lin

Cheng-Hui Weng

Ming-Hsing Tsai

Yen-Chun Lin

Kai-Shiang Kuo

Chien Chung Huang

Chain-Shu Hsu

Kuan-Chia Chen

Chih-Yi Chang

Huei-Wen Hsieh

Jhong-Sian Wu

Cheng-Lun Tsai

Wen-Hsuan Chen

Ming-Yuan Gao

Hsin-Ying Peng

Chien-Lung Wang

Jyun-Fong Jheng

Ching-Yang Liu

Huan-yu Shih

Ming-Chou Chiang

Jau-Jiun Huang

Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

Semiconductor devices and methods of formation

A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.

Interconnect structure of semiconductor device

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Semiconductor device having a contact structure

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Ruthenium-based liner for a copper interconnect

A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

Method of making a contact structure

A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Diffusion barrier for semiconductor device and method

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

Contact structure and method of making

A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.

An organic semiconductor material is provided. The organic semiconductor material includes a compound represented by formula (1): wherein r and s each independently represent a positive integer of 1 to 20; n represents a positive integer of 2 to 10000; X, Xand Xeach independently represent O, S, Se, Te, NR, RCR, RSiR, RGeR or RSnR; Yand Yeach independently represent H, F, Cl, CF, haloalkyl, CN, R, OR, SR, COOR or COR; and Z, Z, Zand Zeach independently represent H, F, Cl, CF, haloalkyl, CN, R, OR, SR, COOR or COR, wherein R represents alkyl group.

Organic semiconductor material and thin-film transistor

Growing community of inventors

Taipei, Taiwan

Yao-Min Liu