Taiwan Semiconductor Manufacturing Comp. Ltd.

Yao-Ling Huang

Hou-Yu Chen

Chih-Kuan Yu

Chung-Pin Huang

Chuan-Li Chen

A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Semiconductor device and manufacturing method thereof

A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

A method includes forming a first gate, a second gate, a third gate, and a fourth gate over a substrate, in which a first distance between the first gate and the second gate is less than a second distance between the third gate and the fourth gate. A first spacer over a sidewall of the first gate, a second spacer over a sidewall of the second gate, a third spacer over a sidewall of the third gate, and a fourth spacer over a sidewall of the fourth gate are formed. A mask layer over the first and second spacers is formed, in which the third and fourth spacers are exposed from the mask layer. The exposed third and fourth spacers are trimmed.

A semiconductor device includes a substrate; a first device disposed on the substrate, and the first device includes at least two first gate stacks, in which the two adjacent first gate stacks have a first distance therebetween; a plurality of first gate spacers having a first thickness disposed on opposite sidewalls of the first gate stacks; the semiconductor device further includes a second device disposed on the substrate, and the second device includes at least two second gate stacks, in which the two adjacent second gate stacks have a second distance therebetween, and the first distance is smaller than the second distance; a plurality of second gate spacers having a second thickness disposed on opposite sidewalls of the second gate stacks, and the first thickness is greater than the second thickness.

Growing community of inventors

Zhubei, Taiwan

Yao-Ling Huang