Synopsys, Inc.

Yao-Jih Hung

Wei-Cheng Chen

Robert Cameron Doig

Jen-Feng Huang

Chi-Liang Yang

Yung Le Wang

Chia-Hsuan Cheng

A method for generating a circuit layout includes generating a plurality of symbols. Each of the plurality of symbols identifies one of multiple versions of code describing a circuit layout. The method also includes loading the plurality of symbols into a design platform used to compile the code describing the circuit layout. The design platform has evaluators for the multiple versions of the code. The method further includes generating the circuit layout described by the code using the design platform.

Integrated circuit design and layout with multiple interpreters

A computer-implemented method is disclosed for speeding up database access of electronic design automation (EDA) tool which utilizes a database manager for file access. The EDA tool accesses a plurality of design files, and each of the plurality of design files is associated with one of a plurality of design units for an integrated circuit (IC). The plurality of design files are encapsulated into an archive file which comprises a plurality of data units, wherein each of the data units corresponds to a design file. A request to access a design file will be redirected to access the archive file. The design file is then accessed by accessing the corresponding data unit in the archive file.

Method of speeding up access to design databases having large numbers of design units

Growing community of inventors

Hsinchu County, Taiwan

Yao-Jih Hung