Taiwan Semiconductor Manufacturing Comp. Ltd.

Yao-Jen Yang

Meng-Sheng Chang

Yih Wang

Shao-Yu Chou

Min-Shin Wu

Chia-En Huang

Chien-Ying Chen

Chia-en Huang

Fu-An Wu

Chen-Ming Hung

Wan-Hsueh Cheng

Hsiang-Wei Liu

Yen-Jen Chen

Chieh Lee

Liang Chuan Chang

Shao-Tung Peng

Jonathan Tsung-Yung Chang

Yi-Ching Liu

Chun-Ying Lee

Andy Yang

Rose Tseng

Ji Kuan Lee

Min-Chiao Yeh

A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

Memory device with improved anti-fuse read current

A memory device includes a plurality of one-time-programmable (OTP) memory cells formed as a memory array. Each of the plurality of OTP memory cells includes a transistor and a metal structure electrically coupled to each other in series, and the plurality of OTP memory cells are formed on a first side of a substrate. The memory device includes a heater structure, disposed on a second side of the substrate opposite to the first side, that includes a plurality of interconnect structures. The plurality of interconnect structures are configured to conduct a substantially high current so as to elevate a temperature of the resistor when any of the OTP memory cells is being programmed.

Semiconductor memory devices with backside heater structure

A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.

Memory device and manufacturing method and test method of the same

A memory device includes a bit line, a source line, a program word line, a read word line, a memory cell including a program transistor and a read transistor, and a controller. The program transistor includes a gate terminal coupled to the program word line, a first terminal coupled to the source line, and a second terminal. The read transistor includes a gate terminal coupled to the read word line, a first terminal coupled to the bit line, and a second terminal coupled to the second terminal of the program transistor. The controller is configured to, in a programming operation, cause a program current to flow through the memory cell along a first current path. The controller is further configured to, in a read operation, cause a read current to flow through the memory cell along a second current path different from the first current path.

Memory device and methods

An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.

Memory device, layout, and method

In one aspect of the present disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes a first conductive structure extending in a first direction, the first conductive structure coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed over, in a third direction perpendicular to the first direction and the second direction, the first conductive structure; and a via structure disposed over the second conductive structure and in contact with the dielectric material, wherein the dielectric material is configured to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Metal fuse structure by via landing

An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Modified fuse structure and method of use

A memory device includes a plurality of memory cells, each of which includes a first transistor, a second transistor, and a resistor operatively coupled to each other in series. Each of the first and second transistors include a sub-transistor, the sub-transistor having a channel structure, a source structure disposed on one side of the channel structure, and a drain structure disposed on the other side of the channel structure. The resistor includes a metal structure disposed above the first and second transistors. The channel structures, source structures, and drain structures of the sub-transistors are all formed in a first active region of a substrate.

One-time-programmable memory devices having first transistor, second transistor, and resistor in series

A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Method of manufacturing semiconductor device

A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Semiconductor device

An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.

Anti-fuse device and method

A device includes a substrate, a first sense amplifier disposed on the substrate, a first word line driver disposed on the substrate and situated adjacent the first sense amplifier in the x-direction, and a first memory array disposed above the first sense amplifier and above the first word line driver in the z-direction. A plurality of first conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first sense amplifier and configured to electrically connect the first sense amplifier to a first bit line of the first memory array. A plurality of second conductive segments extend alternately in the x-direction and the y-direction, and are disposed between the first memory array and the first word line driver and configured to electrically connect the first word line driver to a first word line of the first memory array.

Memory array connections

A memory device includes a first programming gate-strip for a first anti-fuse structure and a second programming gate-strip for a second anti-fuse structure. In the memory device, a terminal conductor overlies a terminal region between the channel regions of a first transistor and a second transistor. The memory device also includes a group of first programming conducting and a group of second programming conducting lines. The first programming conducting lines are conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors. The second programming conducting lines are conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors.

A metal fuse structure may be provided. The metal fuse structure may comprise a first fuse element and a second fuse element. The second fuse element may be adjacent to the first fuse element for a length L. The second fuse element may be spaced apart from first fuse element by a width W.

Efuse with fuse walls and method of manufacturing the same

An integrated circuit includes a transistor formed in a semiconductor structure, a front-side horizontal conducting line in a first metal layer above the semiconductor structure, and a front-side vertical conducting line in a second metal layer above the first metal layer. The front-side horizontal conducting line is directly connected to a first terminal of the transistor, and the front-side vertical conducting line is directly connected to the front-side horizontal conducting line. In the integrated circuit, a front-side fuse element is conductively connected to the front-side vertical conducting line, and a backside conducting line is directly connected to a second terminal of the transistor. A word connection line extending in the first direction is directly connected to a gate terminal of the transistor.

Growing community of inventors

Hsinchu, Taiwan

Yao-Jen Yang