Intel Corporation

Yao Huo

Weigang Li

Junyuan Wang

Kaijie Guo

Maksim Lukoshkov

Zijuan Fan

Ned M Smith

Michael E Kounavis

Ashok Raj

Xin Zeng

Liang J Ma

Songwu Shen

Laurent Coquerel

Brian Will

Qianjun Xie

Yuan Wang

An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

PASID granularity resource control for IOMMU

Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit () is coupled between an input-output memory management unit (IOMMU) () and an endpoint device (). The inspection unit () stores a registry () comprising entries () which each correspond to a respective address, and a respective one or more resources of the endpoint device (). A given entry () of the registry () is created based on a message from the IOM MU () which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device () performs a search, based on a DMA request, to determine if any registry () entry () indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU () is contingent on a result of the search.

Device, system, and method for inspecting direct memory access requests

Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

Address translation technologies

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Shanghai, China

Yao Huo