Stichting Imec Nederland

Imec Vzw

Vrije Universiteit Brussel

Technische Universiteit Delft

Yao-Hong Liu

Marco Mercuri

Paul Mateman

Ming Ding

Minyoung Song

Wilfried Zomagboguelou

Robert Bogdan Staszewski

Jan Craninckx

Johan Van Den Heuvel

Nereo Markulic

Barundeb Dutta

Takashi Kuramochi

Zhihao Zhou

Fabio Sebastiano

Vijay Kumar Purushothaman

Wilhelmus Matthias Clemens Dolmans

Johannes Henricus Cornelus Van Den Heuvel

The present disclosure relates to a brain-computer interface system and method. In an example, a brain-computer interface system includes a data processing unit, a data transceiver unit, and a sensing or stimulation unit. The system also includes a first communication path between the data transceiver unit and the sensing or stimulation unit including a first downlink channel for transmitting power and data from the data transceiver unit to the data sensing unit and a first uplink channel for transmitting data from the sensing or stimulation unit to the data transceiver unit. The system may additionally include a second communication path between the data processing unit and the data transceiver unit including a second downlink channel for transmitting power and data from the data processing unit to the data transceiver unit and a second uplink channel for transmitting data from the data transceiver unit to the data processing unit.

Brain-computer interface system

An event-driven transmission method comprises converting at least one event to at least one corresponding pulse pair and transmitting the at least one pulse pair. In this context, a delay between each pulse pair represents a corresponding identifier with respect to the respective event or with respect to at least one corresponding object causing or experiencing the respective event.

Event-driven transmission method and device

A method of generating an impulse for impulse radio transmission signals and an impulse-radio ultra-wideband transmitter are provided. In one aspect, the method includes distributing input digital data according to time information data and amplitude information data along a first modulation path and a second modulation path, respectively. Pulse position modulation is performed based on the time information data along the first modulation path to define a timing position of the impulse. Pulse amplitude modulation is performed based on the amplitude information data along the second modulation path to define an envelope of the impulse. The input digital data can be distributed according to phase information data along a third modulation path, and phase shift keying modulation can be performed based on the phase information data along the third modulation path to define a phase of a carrier signal of the impulse.

Impulse generation method and impulse-radio transmitter

Example embodiments relate to radar transceivers. One embodiment includes a radar transceiver. The radar transceiver includes a chirp generator for generating a chirp having an initial frequency and a final frequency. The radar transceiver also includes a controllable variable gain amplifier having an input connected to an output of the chirp generator. Further, the radar transceiver includes a control unit connected to a control input on the chirp generator and to a control input on the controllable variable gain amplifier. The control unit is adapted to output a first control signal to the chirp generator such that the chirp generator starts generating the chirp. The control unit is also adapted to output a second control signal to the controllable variable gain amplifier such that the controllable variable gain amplifier starts increasing an amplification in the controllable variable gain amplifier from a first amplification level to a second amplification level.

Radar transceiver

A system is provided for generating a time reference in duty-cycled wireless communications. The system includes at least one master module including a master transceiver adapted to transmit data packets. The system further includes at least one slave module including a slave transceiver adapted to receive the data packets. The slave module further includes a signal generator adapted to generate a clock signal with a period equal to the time interval of two data packets transmitted by the master module. Moreover, the slave module further includes a slave timer adapted to utilize the clock signal as a time reference in order to perform the sleep/wakeup control for the slave module.

System and method for generating time reference in duty-cycled wireless communications

Example embodiments relate to methods for adjusting an impedance of a tunable matching network, One embodiment includes a method for adjusting an impedance of a tunable matching network (TMN) connected between an antenna and a transceiver front-end. The TMN includes a receive path to provide signals from the antenna to a receiver during a receive (Rx) mode and a transmit path to provide signals from a transmitter to the antenna during a transmit (Tx) mode. The method includes tuning the TMN. The method also includes measuring values of an output DC-offset at the receiver while tuning the TMN. The output DC-offset is caused by a coupling between the transmitter and the receiver. Further, the method includes determining a maximum value of the output DC-offset from the measured output DC-offset values. Additionally, the method includes adjusting the impedance of the TMN by tuning the TMN to the output DC-offset maximum value.

Method for adjusting an impedance of a tunable matching network

A signal generator is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components, each control component of the set being arranged to be switchably activated in parallel in the circuitry such that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling activation of a respective control component of the set of control components such that the control components are arranged to be activated or de-activated in a pre-determined order by shifting activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

Amplitude sweep generator and method

A method of detecting a vital sign comprising at least one of a heart rate and a respiratory rate of a subject is provided. In one aspect, the method includes transmitting a radio frequency signal towards the subject; and receiving a reflected signal from the subject, wherein the transmitted signal is reflected by the subject and Doppler-shifted due to at least one of the heart rate and the respiratory rate to form the reflected signal. The method also includes mixing the reflected signal with a first reference signal; and providing a vital sign carrying signal based on the mixing to a first input of a phase or frequency comparator. The method further includes generating an adjustable second reference signal and providing the reference signal to a second input of the phase or frequency comparator; and generating an output signal, by the phase or frequency comparator. The method includes varying at least one of a phase and a frequency of the adjustable second reference signal based on the output signal to track a phase or frequency of the vital sign carrying signal.

Method and device for detecting a vital sign carrying signal using a phase-locked loop

An oscillator is configured to generate a signal with a frequency sweep, the oscillator having circuitry comprising a set of capacitors, each capacitor of the set of capacitors being switchably connectable in parallel in the circuitry so that the frequency of the signal has an intrinsic dependence on the number of the capacitors connected, a shift register controllable by a clock line and comprising a number of bits, each bit of the number of bits controlling connection of a respective capacitor of the set of capacitors so that the capacitors are connectable or disconnectable in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator configured to output a clock signal with a time modulation on the clock line.

Frequency sweep generator and method

A method and system for detecting at least one of a heart rate and a respiratory rate of a subject are disclosed. In one aspect, the method includes transmitting a signal towards the subject and receiving a reflected signal from the subject being Doppler-shifted due to at least one of the heart rate and the respiratory rate. The method also includes providing the reflected signal to a first input of a phase comparator, providing an adjustible reference signal to a second input of the phase comparator, and generating an output signal by the phase comparator based on the reflected signal and the reference signal. The method includes varying, by the reference signal generator, at least one of a phase and a frequency of the adjustable reference signal based on the output signal of the phase comparator to track a phase of the reflected signal.

Method for detecting at least one of a heart rate and a respiratory rate of a subject

Example embodiments relate to transceiver devices with real-time clocks. One embodiment includes a transceiver device. The transceiver device includes a real-time clock arranged for providing a clock signal. The transceiver device also includes a receiving section. The receiving section includes a main receiver arranged for receiving communication signals. The receiving section also includes a wake-up receiver. The wake-up receiver is arranged for receiving a calibration signal that includes clock timing information containing a time stamp. The wake-up receiver is also arranged for adjusting the real-time clock based on the clock timing information.

Transceiver device with real-time clock

The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.

Wakeup timer using bang-bang digital-intensive frequency locked-loop

The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Digital phase locked loop and method for operating the same

The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.

DTC-based PLL and method for operating the DTC-based PLL

The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

Growing community of inventors

Eindhoven, Netherlands

Yao-Hong Liu